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CA-IS3762LW

Public Made by Adom

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Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsca-is3762lwfactory-2.0.0extractor-text

Verified CA-IS3762LW

by Ray · last 12 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

12 Nov 2026RayPublished by the parts factory: tier lcsc, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CA-IS3762LW · SOIC-16-300mil · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 22-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-16W_7.5x10.3mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-13w3li43/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.19)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 33 kB, viewers/symbol.html 14 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ca-is3762lw.kicad_sym✓ ca-is3762lw.kicad_mod✓ ca-is3762lw.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers ca-is3762lw: viewers rendered from the public page · Ray
ca-is3762lw-etched.glb Publish 0.1.0 · Ray
ca-is3762lw-etched.step ca-is3762lw: factory component page (tier=lcsc) · Ray
ca-is3762lw-hero.glb ca-is3762lw: hero GLB from the etched model (keeps the MPN mark) · Ray
ca-is3762lw-hero.overlay.json ca-is3762lw: hero GLB from the etched model (keeps the MPN mark) · Ray
ca-is3762lw.glb Publish 0.1.0 · Ray
ca-is3762lw.kicad_mod Publish 0.1.0 · Ray
ca-is3762lw.kicad_sym Publish 0.1.0 · Ray
ca-is3762lw.lbr Publish 0.1.0 · Ray
ca-is3762lw.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 16 pins · Ray

CA-IS3762LW

Chipanalog · Digital Isolators · SOIC-16-300mil

CA-IS3762LW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in A-side supply voltage, specified from 2.375 V to 5.5 V in the recommended operating conditions, with 0.1 µF to 1 µF bypass capacitors recommended.
2 VI1 input A-side logic input of forward channel 1, a Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V.
3 VI2 input A-side logic input of forward channel 2, a Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V.
4 VI3 input A-side logic input of forward channel 3, a Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V.
5 VI4 input A-side logic input of forward channel 4 on CA-IS3762, a Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V.
6 VO5 output A-side logic output of reverse channel 5 on CA-IS3762, a rail-to-rail output with about 50 Ω output impedance.
7 VO6 output A-side logic output of reverse channel 6 on CA-IS3762, a rail-to-rail output with about 50 Ω output impedance.
8 GNDA power_in A-side ground reference point for the A-side signals and supply.
9 GNDB power_in B-side ground reference point, isolated from GNDA.
10 VI6 input B-side logic input of reverse channel 6 on CA-IS3762, a Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V.
11 VI5 input B-side logic input of reverse channel 5 on CA-IS3762, a Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V.
12 VO4 output B-side logic output of forward channel 4 on CA-IS3762, a rail-to-rail output with about 50 Ω output impedance.
13 VO3 output B-side logic output of forward channel 3, a rail-to-rail output with about 50 Ω output impedance.
14 VO2 output B-side logic output of forward channel 2, a rail-to-rail output with about 50 Ω output impedance.
15 VO1 output B-side logic output of forward channel 1, a rail-to-rail output with about 50 Ω output impedance.
16 VDDB power_in B-side supply voltage, specified from 2.375 V to 5.5 V in the recommended operating conditions, with 0.1 µF to 1 µF bypass capacitors recommended.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16-300mil
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB VDDA, VDDB 2.375 3.3 5.5 V 5
UVLO rising threshold VDD(UVLO+) 1.95 2.24 2.375 V VDD rising 5
UVLO falling threshold VDD(UVLO-) 1.88 2.1 2.325 V VDD falling 5
UVLO hysteresis VHYS(UVLO) 70 140 250 mV 5
High-level output current IOH -4 mA VDDO1 = 5V 5
High-level output current IOH -2 mA VDDO = 3.3V 5
High-level output current IOH -1 mA VDDO = 2.5V 5
Low-level output current IOL 4 mA VDDO = 5V 5
Low-level output current IOL 2 mA VDDO = 3.3V 5
Low-level output current IOL 1 mA VDDO = 2.5V 5
Input threshold logic high VIH 2 V 5
Input threshold logic low VIL 0.8 V 5
Signal data rate DR 0 150 Mbps 5
Ambient temperature TA -40 27 125 °C 5
Supply voltage VDDA, VDDB VDDA, VDDB -0.5 6 V 5
Input voltage Vin -0.5 V Ax, Bx, ENx; max VDDA+0.5 V (not to exceed 6 V, note 3) 5
Output current IO -20 20 mA 5
Junction temperature TJ 150 °C 5
Storage temperature range TSTG -65 150 °C 5
Output voltage logic low VOL 0.2 0.4 V IOL = 4mA; VDDA=VDDB=5 V ±10% 9
Positive input threshold VIT+(IN) 1.4 1.67 1.9 V VDDA=VDDB=5 V ±10% 9
Negative input threshold VIT-(IN) 1 1.23 1.4 V VDDA=VDDB=5 V ±10% 9
Input threshold hysteresis VI(HYS) 0.3 0.44 0.5 V VDDA=VDDB=5 V ±10% 9
Input high leakage current IIH 4 µA VIH = VDDA at Ax or Bx or ENx; VDDA=VDDB=5 V ±10% 9
Input low leakage current IIL -4 µA VIL = 0 V at Ax or Bx; VDDA=VDDB=5 V ±10% 9
Common-mode transient immunity CMTI 75 100 kV/µs VI = VDDI1 or 0 V, VCM = 1200 V; Fig 7-3; VDDA=VDDB=5 V ±10% 9
Minimum pulse width PWmin 5 ns VDDA=VDDB=5 V ±10% 13
Propagation delay tPLH, tPHL 5 8 13 ns Fig 7-1; VDDA=VDDB=5 V ±10% 13
Pulse width distortion PWD 0.2 4.5 ns /tPLH - tPHL/; VDDA=VDDB=5 V ±10% 13
Default output delay time from input power loss tDO 8 12 ns Fig 7-2; VDDA=VDDB=5 V ±10% 13
Startup time tSU 15 40 µs VDDA=VDDB=5 V ±10% 13
Pulse width distortion PWD 0.2 5 ns /tPLH - tPHL/; VDDA=VDDB=2.5 V ±5% 13
Junction-to-ambient thermal resistance (W, SOIC16 wide body) RθJA 83.4 °C/W 6
Junction-to-case (top) thermal resistance (W, SOIC16 wide body) RθJC(top) 46 °C/W 6
Junction-to-board thermal resistance (W, SOIC16 wide body) RθJB 48 °C/W 6
Junction-to-top characterization parameter (W, SOIC16 wide body) ψJT 19.1 °C/W 6
Junction-to-board characterization parameter (W, SOIC16 wide body) ψJB 47.5 °C/W 6

CAD (KiCad official)

  • Symbol: CA-IS3762LW
  • Footprint: Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ca-is3762lw-etched.step / ca-is3762lw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3762lw.step / ca-is3762lw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (22 pp, sha256 adf22151c4806ef6, retrieved 2026-11-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF