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CA-IS3761LW

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Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CA-IS3761LW

Chipanalog · Digital Isolators · SOIC-16-300mil

CA-IS3761LW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side-A supply voltage, recommended 2.375 V to 5.5 V, with absolute maximum 6.0 V relative to GNDA; place a 0.1 µF to 1 µF bypass capacitor within 2 mm of the pin.
2 VI1 input Side-A logic input for forward channel 1, Schmitt-trigger input compatible with CMOS and TTL levels (VIH 2.0 V min, VIL 0.8 V max at 5 V).
3 VI2 input Side-A logic input for forward channel 2, Schmitt-trigger input compatible with CMOS and TTL levels (VIH 2.0 V min, VIL 0.8 V max at 5 V).
4 VI3 input Side-A logic input for forward channel 3, Schmitt-trigger input compatible with CMOS and TTL levels (VIH 2.0 V min, VIL 0.8 V max at 5 V).
5 VI4 input Side-A logic input for forward channel 4 on the CA-IS3761 (pin is an output on CA-IS3763), Schmitt-trigger input with about 2 pF input capacitance and leakage limited to ±4 µA.
6 VI5 input Side-A logic input for forward channel 5 on the CA-IS3761 (pin is an output on CA-IS3762/63), Schmitt-trigger input with leakage limited to ±4 µA.
7 VO6 output Side-A logic output for reverse channel 6 on the CA-IS3761, a rail-to-rail output with about 50 Ω output impedance and ±4 mA drive at 5 V supply.
8 GNDA power_in Side-A ground reference for the isolator's A-side circuits; all A-side voltages are referenced to this pin.
9 GNDB power_in Side-B ground reference for the isolator's B-side circuits; all B-side voltages are referenced to this pin.
10 VI6 input Side-B logic input for reverse channel 6 on the CA-IS3761, Schmitt-trigger input with leakage limited to ±4 µA.
11 VO5 output Side-B logic output for forward channel 5 on the CA-IS3761, a rail-to-rail output with about 50 Ω output impedance and ±4 mA drive at 5 V supply.
12 VO4 output Side-B logic output for forward channel 4 on the CA-IS3761, a rail-to-rail output with about 50 Ω output impedance and ±4 mA drive at 5 V supply.
13 VO3 output Side-B logic output for forward channel 3, a rail-to-rail output with about 50 Ω output impedance and ±4 mA drive at 5 V supply.
14 VO2 output Side-B logic output for forward channel 2, a rail-to-rail output with about 50 Ω output impedance and ±4 mA drive at 5 V supply.
15 VO1 output Side-B logic output for forward channel 1, a rail-to-rail output with about 50 Ω output impedance and ±4 mA drive at 5 V supply.
16 VDDB power_in Side-B supply voltage, recommended 2.375 V to 5.5 V, with absolute maximum 6.0 V relative to GNDB; place a 0.1 µF to 1 µF bypass capacitor within 2 mm of the pin.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB VDDA, VDDB 2.375 3.3 5.5 V 5
Undervoltage threshold, rising VDD VDD(UVLO+) 1.95 2.24 2.375 V VDD rising 5
Undervoltage threshold, falling VDD VDD(UVLO-) 1.88 2.1 2.325 V VDD falling 5
UVLO hysteresis VHYS(UVLO) 70 140 250 mV 5
High-level output current IOH -4 mA VDDO = 5 V 5
High-level output current IOH -2 mA VDDO = 3.3 V 5
High-level output current IOH -1 mA VDDO = 2.5 V 5
Low-level output current IOL 4 mA VDDO = 5 V 5
Low-level output current IOL 2 mA VDDO = 3.3 V 5
Low-level output current IOL 1 mA VDDO = 2.5 V 5
Input threshold logic high VIH 2 V 5
Input threshold logic low VIL 0.8 V 5
Signaling data rate DR 0 150 Mbps 5
Ambient temperature TA -40 27 125 °C 5
Supply voltage VDDA, VDDB VDDA, VDDB -0.5 6 V Relative to local ground (GNDA or GNDB) 5
Input voltage Vin -0.5 V Ax, Bx, ENx; printed as VDDA+0.5, maximum not to exceed 6 V 5
Output current IO -20 20 mA 5
Junction temperature TJ 150 °C 5
Storage temperature range TSTG -65 150 °C 5
High-level output voltage VOH 4.8 V IOH = -4 mA; Fig 7-1; min printed as VDDO1-0.4 V 9
Low-level output voltage VOL 0.2 0.4 V IOL = 4 mA; Fig 7-1 9
Positive input threshold VIT+(IN) 1.4 1.67 1.9 V 9
Negative input threshold VIT-(IN) 1 1.23 1.4 V 9
Input threshold hysteresis VI(HYS) 0.3 0.44 0.5 V 9
Input high-level leakage current IIH 4 µA VIH = VDDA at Ax or Bx or ENx 9
Input low-level leakage current IIL -4 µA VIL = 0 V at Ax or Bx 9
Output impedance ZO 50 Ω 9
Common-mode transient immunity CMTI 75 100 kV/µs VI = VDDI1 or 0 V, VCM = 1200 V; Fig 7-3 9
Input capacitance CI 2 pF VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V 9
Supply current IDDA, CA-IS3761L, DC input low IDDA 1.9 2.9 mA VIN = 0 V (CA-IS3761L); VIN = VDDI (CA-IS3761H); 5 V ±10% 10
Supply current IDDB, CA-IS3761L, DC input low IDDB 2.9 5.9 mA VIN = 0 V (CA-IS3761L); VIN = VDDI (CA-IS3761H); 5 V ±10% 10
Supply current IDDA, CA-IS3761L, DC input high IDDA 5.7 8.5 mA VIN = VDDI (CA-IS3761L); VIN = 0 V (CA-IS3761H); 5 V ±10% 10
Supply current IDDB, CA-IS3761L, DC input high IDDB 4.9 7.3 mA VIN = VDDI (CA-IS3761L); VIN = 0 V (CA-IS3761H); 5 V ±10% 10
Supply current IDDA, AC 1 Mbps IDDA 3.9 5.8 mA 1 Mbps (500 kHz); all channels 50% duty 5 V square wave; CL = 15 pF; 5 V ±10% 10
Supply current IDDB, AC 1 Mbps IDDB 4.7 7 mA 1 Mbps (500 kHz); all channels 50% duty 5 V square wave; CL = 15 pF; 5 V ±10% 10
Supply current IDDA, AC 10 Mbps IDDA 4.4 6.5 mA 10 Mbps (5 MHz); all channels 50% duty 5 V square wave; CL = 15 pF; 5 V ±10% 10
Supply current IDDB, AC 10 Mbps IDDB 7 10.5 mA 10 Mbps (5 MHz); all channels 50% duty 5 V square wave; CL = 15 pF; 5 V ±10% 10
Supply current IDDA, AC 100 Mbps IDDA 9.1 13.7 mA 100 Mbps (50 MHz); all channels 50% duty 5 V square wave; CL = 15 pF; 5 V ±10% 10
Supply current IDDB, AC 100 Mbps IDDB 30.8 46.2 mA 100 Mbps (50 MHz); all channels 50% duty 5 V square wave; CL = 15 pF; 5 V ±10% 10
Minimum pulse width PWmin 5 ns 13
Data rate DR 0 150 Mbps 5 V ±10% 13
Propagation delay tPLH, tPHL 5 8 13 ns Fig 7-1 13
Pulse width distortion PWD 0.2 4.5 ns /tPLH - tPHL/ 13
Channel-to-channel output skew, same direction tsk(o) 0.4 2.5 ns Same-direction channels 13
Part-to-part channel output skew tsk(pp) 2 4.5 ns Part to part, same direction 13
Output rise time tr 2.5 4 ns Fig 7-1 13
Output fall time tf 2.5 4 ns Fig 7-1 13
Default output delay time from input power loss tDO 8 12 ns Fig 7-2 13
Startup time tSU 15 40 µs 13
Junction-to-ambient thermal resistance, SOIC-16 wide body RθJA 83.4 °C/W W (SOIC) 16 pins 6
Junction-to-case (top) thermal resistance, SOIC-16 wide body RθJC(top) 46 °C/W W (SOIC) 16 pins 6
Junction-to-board thermal resistance, SOIC-16 wide body RθJB 48 °C/W W (SOIC) 16 pins 6
Junction-to-top characterization parameter, SOIC-16 wide body ψJT 19.1 °C/W W (SOIC) 16 pins 6
Junction-to-board characterization parameter, SOIC-16 wide body ψJB 47.5 °C/W W (SOIC) 16 pins 6

CAD (KiCad official)

  • Symbol: CA-IS3761LW
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ca-is3761lw-etched.step / ca-is3761lw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3761lw.step / ca-is3761lw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (22 pp, sha256 adf22151c4806ef6, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF