component
CA-IS3742LB
Public Made by Adomby adom
Chipanalog Digital Isolators, SSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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CA-IS3742LB
Chipanalog · Digital Isolators · SSOP-16
CA-IS3742LB from Chipanalog, in a SSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | A-side supply voltage, recommended 2.375 V to 5.5 V (absolute maximum 7.0 V); bypass to GNDA with a 0.1 µF to 1 µF capacitor placed close to the pin. |
| 2 | GNDA | power_in | A-side ground reference; all A-side signals are referenced to this pin. |
| 3 | VI1 | input | A-side logic input for forward channel 1, Schmitt-trigger input with TTL-compatible thresholds (VIH min 2.0 V, VIL max 0.8 V). |
| 4 | VI2 | input | A-side logic input for forward channel 2, Schmitt-trigger input with TTL-compatible thresholds (VIH min 2.0 V, VIL max 0.8 V). |
| 5 | VO3 | output | A-side logic output of channel A3 (CA-IS3742); enabled by ENA and goes high-impedance when ENA is low. |
| 6 | VO4 | output | A-side logic output of channel A4 (CA-IS3742); enabled by ENA and goes high-impedance when ENA is low. |
| 7 | ENA | input | A-side active-high output enable with internal pull-up to local VDD; drive it to an external logic level in noisy environments rather than leaving it floating with traces attached. |
| 8 | GNDA | power_in | A-side ground reference, internally tied to pin 2 GNDA. |
| 9 | GNDB | power_in | B-side ground reference; all B-side signals are referenced to this pin. |
| 10 | ENB | input | B-side active-high output enable with internal pull-up to local VDD; when low, outputs B1 and B2 go high-impedance. |
| 11 | VI4 | input | B-side logic input for reverse channel 4 (CA-IS3742), Schmitt-trigger input with TTL-compatible thresholds. |
| 12 | VI3 | input | B-side logic input for reverse channel 3 (CA-IS3742), Schmitt-trigger input with TTL-compatible thresholds. |
| 13 | VO2 | output | B-side logic output of channel B2; enabled by ENB and high-impedance when ENB is low. |
| 14 | VO1 | output | B-side logic output of channel B1; enabled by ENB and high-impedance when ENB is low. |
| 15 | GNDB | power_in | B-side ground reference, internally tied to pin 9 GNDB. |
| 16 | VDDB | power_in | B-side supply voltage, recommended 2.375 V to 5.5 V (absolute maximum 7.0 V); bypass to GNDB with a 0.1 µF to 1 µF capacitor placed close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SSOP-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDDA, VDDB | VDDA, VDDB | 2.375 | 5.5 | V | 5 | ||
| UVLO threshold, VDD rising | VDD(UVLO+) | 1.95 | 2.24 | 2.37 | V | 5 | |
| UVLO threshold, VDD falling | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | 5 | |
| UVLO hysteresis | VHYS(UVLO) | 70 | 140 | 250 | mV | 5 | |
| High-level output current | IOH | -4 | mA | VDDO = 5V | 5 | ||
| High-level output current | IOH | -2 | mA | VDDO = 3.3V | 5 | ||
| High-level output current | IOH | -1 | mA | VDDO = 2.5V | 5 | ||
| Low-level output current | IOL | 4 | mA | VDDO = 5V | 5 | ||
| Low-level output current | IOL | 2 | mA | VDDO = 3.3V | 5 | ||
| Low-level output current | IOL | 1 | mA | VDDO = 2.5V | 5 | ||
| Input threshold logic high | VIH | 2 | V | 5 | |||
| Input threshold logic low | VIL | 0.8 | V | 5 | |||
| Signal data rate | DR | 0 | 150 | Mbps | 5 | ||
| Ambient operating temperature | TA | -40 | 27 | 125 | °C | 5 | |
| Supply voltage VDDA, VDDB (absolute maximum) | VDDA, VDDB | -0.5 | 7 | V | 5 | ||
| Input voltage Ax, Bx, ENx (max VDD+0.5, printed as VDD+0.53) | Vin | -0.5 | V | 5 | |||
| Output current | IO | -20 | 20 | mA | 5 | ||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 5 | ||
| Logic low output voltage (5 V) | VOL | 0.2 | 0.4 | V | IOL = 4mA; 图 8-2 | 9 | |
| Input threshold logic high (5 V) | VIT+(IN) | 2 | V | 9 | |||
| Input threshold logic low (5 V) | VIT-(IN) | 0.8 | V | 9 | |||
| Input high-level leakage current (5 V) | IIH | 20 | µA | VIH = VDDA at Ax or Bx or ENx | 9 | ||
| Input low-level leakage current (5 V) | IIL | -20 | µA | VIL = 0 V at Ax or Bx or ENx | 9 | ||
| Output impedance tolerance (5 V; note 2: 50 Ω ±40%) | ZO | -40 | 40 | % | Output impedance ±40% (note 2) | 9 | |
| Common-mode transient immunity (5 V) | CMTI | 100 | 150 | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-4 | 9 | |
| Logic low output voltage (3.3 V) | VOL | 0.2 | 0.4 | V | IOL = 2mA; 图 8-2 | 9 | |
| Input threshold logic high (3.3 V) | VIT+(IN) | 2 | V | 9 | |||
| Input threshold logic low (3.3 V) | VIT-(IN) | 0.8 | V | 9 | |||
| Input high-level leakage current (3.3 V) | IIH | 20 | µA | VIH = VDDA at Ax or Bx or ENx | 9 | ||
| Input low-level leakage current (3.3 V) | IIL | -20 | µA | VIL = 0 V at Ax or Bx or ENx | 9 | ||
| Output impedance tolerance (3.3 V; note 2: 50 Ω ±40%) | ZO | -40 | 40 | % | Output impedance ±40% (note 2) | 9 | |
| Common-mode transient immunity (3.3 V) | CMTI | 100 | 150 | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-4 | 9 | |
| Logic low output voltage (2.5 V) | VOL | 0.2 | 0.4 | V | IOL = 1mA; 图 8-2 | 9 | |
| Input threshold logic high (2.5 V) | VIT+(IN) | 2 | V | 9 | |||
| Input threshold logic low (2.5 V) | VIT-(IN) | 0.8 | V | 9 | |||
| Input high-level leakage current (2.5 V) | IIH | 20 | µA | VIH = VDDA at Ax or Bx or ENx | 9 | ||
| Input low-level leakage current (2.5 V) | IIL | -20 | µA | VIL = 0 V at Ax or Bx or ENx | 9 | ||
| Output impedance tolerance (2.5 V; note 2: 50 Ω ±40%) | ZO | -40 | 40 | % | Output impedance ±40% (note 2) | 9 | |
| Common-mode transient immunity (2.5 V) | CMTI | 100 | 150 | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-4 | 9 | |
| Minimum pulse width (5 V) | PWmin | 5 | ns | 13 | |||
| Propagation delay (5 V) | tPLH, tPHL | 5 | 12 | 16 | ns | 图 8-1 | 13 |
| Pulse width distortion (5 V) | PWD | 0.2 | 4.5 | ns | /tPLH - tPHL/ | 13 | |
| Channel-to-channel output skew, same direction (5 V) | tsk(o) | 0.4 | 2.5 | ns | 同方向通道 (note 1) | 13 | |
| Part-to-part channel output skew (5 V) | tsk(pp) | 2 | 4.5 | ns | note 2 | 13 | |
| Output rise time (5 V) | tr | 2.5 | 4 | ns | 图 8-1 | 13 | |
| Output fall time (5 V) | tf | 2.5 | 4 | ns | 图 8-1 | 13 | |
| Disable propagation delay, output high to high-Z (5 V) | tPHZ | 8 | 13 | ns | 图 8-2 | 13 | |
| Disable propagation delay, output low to high-Z (5 V) | tPLZ | 8 | 17 | ns | 13 | ||
| Enable propagation delay, high-Z to high (5 V, L variant) | tPZH | 10 | 20 | ns | CA-IS374xL | 13 | |
| Enable propagation delay, high-Z to low (5 V, L variant) | tPZL | 10 | 25 | ns | CA-IS374xL | 13 | |
| Default output delay from input supply reaching UVLO (5 V) | tDO | 8 | 12 | µs | 图 8-3 | 13 | |
| Startup time (5 V) | tSU | 15 | 40 | µs | 13 | ||
| Supply current IDDA, enable off, VIN=0V (5 V, L variant) | IDDA | 2.2 | 3.3 | mA | ENA = ENB = 0 V; VIN = 0V (CA-IS3742L) | 10 | |
| Supply current IDDB, enable off, VIN=0V (5 V, L variant) | IDDB | 2.2 | 3.3 | mA | ENA = ENB = 0 V; VIN = 0V (CA-IS3742L) | 10 | |
| Supply current IDDA, DC signal, VIN=0V (5 V, L variant) | IDDA | 2.4 | 3.5 | mA | ENA = ENB = VDDI; VIN = 0V (CA-IS3742L) | 10 | |
| Supply current IDDB, DC signal, VIN=0V (5 V, L variant) | IDDB | 2.4 | 3.5 | mA | ENA = ENB = VDDI; VIN = 0V (CA-IS3742L) | 10 | |
| Supply current IDDA, 100Mbps (5 V) | IDDA | 24 | 33 | mA | ENA = ENB = VDDI; 100Mbps (50MHz); 50% 5V方波; CL = 15 pF | 10 | |
| Supply current IDDB, 100Mbps (5 V) | IDDB | 24 | 33 | mA | ENA = ENB = VDDI; 100Mbps (50MHz); 50% 5V方波; CL = 15 pF | 10 | |
| Thermal resistance, junction to ambient (SSOP16-NB(B)) | RθJA | 110 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
CA-IS3742LB - Footprint:
Package_SO:SSOP-16_5.3x6.2mm_P0.65mm - 3D model: SSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ca-is3742lb-etched.step/ca-is3742lb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3742lb.step/ca-is3742lb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (25 pp, sha256
fd7bb5373a55db4c, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).