main
Ray Set visibility: public 95965bf 12d ago
{
  "schema_version": 1,
  "type": "component",
  "slug": "ca-is3643hvw",
  "title": "CA-IS3643HVW",
  "brief": "Chipanalog Digital Isolators (With Power), SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "signal isolation devices",
    "ca-is3643hvw",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "CA-IS3643HVW",
    "manufacturer": "Chipanalog",
    "package": "SOIC-16-300mil",
    "pin_count": 16,
    "category": "Signal Isolation Devices",
    "subcategory": "Digital Isolators (With Power)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602993947291627520",
    "parts": {
      "symbol": "ca-is3643hvw.kicad_sym",
      "footprint": "ca-is3643hvw.kicad_mod",
      "model_3d": "ca-is3643hvw-hero.glb",
      "model_3d_plain": "ca-is3643hvw-etched.glb",
      "model_3d_step": "ca-is3643hvw-etched.step",
      "model_3d_step_plain": "ca-is3643hvw.step",
      "lbr": "ca-is3643hvw.lbr"
    },
    "distributor_links": {
      "lcsc": "C7422549"
    },
    "distributor_check": {
      "checked_at": "2026-10-19T10:07:17Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "error"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "A-side supply that powers the internal DC-DC converter, recommended 3.15 V to 5.5 V (5 V typ), with 0.1 µF and 10 µF bypass capacitors placed within 2 mm of the pin."
      },
      {
        "number": "2",
        "name": "GNDA",
        "type": "power_in",
        "description": "A-side ground reference for VDD, VDDL and the A-side logic pins."
      },
      {
        "number": "3",
        "name": "VI1",
        "type": "input",
        "description": "A-side logic input for channel 1 of the CA-IS3643; VIH minimum 2.0 V and VIL maximum 0.8 V."
      },
      {
        "number": "4",
        "name": "VO2",
        "type": "output",
        "description": "A-side logic output for channel 2 of the CA-IS3643, driving at most −4 mA high and 4 mA low at 5 V (−2 mA / 2 mA at 3.3 V)."
      },
      {
        "number": "5",
        "name": "VO3",
        "type": "output",
        "description": "A-side logic output for channel 3 of the CA-IS3643, driving at most −4 mA high and 4 mA low at 5 V (−2 mA / 2 mA at 3.3 V)."
      },
      {
        "number": "6",
        "name": "VO4",
        "type": "output",
        "description": "A-side logic output for channel 4 of the CA-IS3643, driving at most −4 mA high and 4 mA low at 5 V (−2 mA / 2 mA at 3.3 V)."
      },
      {
        "number": "7",
        "name": "VDDL",
        "type": "power_in",
        "description": "Logic supply for the A side (VW variant) that sets the A-side input threshold and output level, recommended 2.375 V to 5.5 V and may differ from VDD."
      },
      {
        "number": "8",
        "name": "GNDA",
        "type": "power_in",
        "description": "A-side ground reference for VDD, VDDL and the A-side logic pins."
      },
      {
        "number": "9",
        "name": "GNDB",
        "type": "power_in",
        "description": "B-side ground reference for VISO and the B-side logic pins."
      },
      {
        "number": "10",
        "name": "SEL",
        "type": "input",
        "description": "VISO output-voltage select: tie to VISO for 5 V, tie to GNDB or leave open for 3.3 V, and do not change its level during start-up."
      },
      {
        "number": "11",
        "name": "VI4",
        "type": "input",
        "description": "B-side logic input for channel 4 of the CA-IS3643, with VIH minimum 2.0 V and VIL maximum 0.8 V."
      },
      {
        "number": "12",
        "name": "VI3",
        "type": "input",
        "description": "B-side logic input for channel 3 of the CA-IS3643, with VIH minimum 2.0 V and VIL maximum 0.8 V."
      },
      {
        "number": "13",
        "name": "VI2",
        "type": "input",
        "description": "B-side logic input for channel 2 of the CA-IS3643, with VIH minimum 2.0 V and VIL maximum 0.8 V."
      },
      {
        "number": "14",
        "name": "VO1",
        "type": "output",
        "description": "B-side logic output for channel 1 of the CA-IS3643, driving at most −4 mA high and 4 mA low at 5 V (−2 mA / 2 mA at 3.3 V)."
      },
      {
        "number": "15",
        "name": "GNDB",
        "type": "power_in",
        "description": "B-side ground reference for VISO and the B-side logic pins."
      },
      {
        "number": "16",
        "name": "VISO",
        "type": "power_out",
        "description": "Isolated output supply of 5 V or 3.3 V set by SEL, with 0.1 µF and 10 µF bypass capacitors placed within 2 mm of the pin to GNDB; maximum load is 110 mA at 100 Mbps with a 5 V output at 25 °C and must be derated above 85 °C."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin-function table (Table 7-2) labels pins 12 and 13 as B-side outputs (VI3/VO3 and VI2/VO2) for; Pin 7 is labelled NC/VDDL on the CA-IS364x drawing. The MPN suffix VW selects the VDDL version, so p; The datasheet gives VDD, VDDL and VISO ranges in a table on page 7 and the VISO output voltage on pa"
        ],
        "pages_sent": 30,
        "cost_usd": 0.167,
        "at": "2026-10-19T10:04:21"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602993947291627520",
        "pages": 39,
        "sha256": "74e1e848c9ed7ac2",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ca-is3643hvw.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ca-is3643hvw-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "e81af915371ae063ed140d2f004fa0f391238b1650b198db24673bcf5aa7c2d9",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Chipanalog",
      "Package": "SOIC-16-300mil",
      "Category": "Signal Isolation Devices",
      "Pins": "16"
    }
  },
  "variants": [],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "ca-is3643hvw"
  ],
  "discovery_pitch": "CA-IS3643HVW (Chipanalog) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ca-is3643hvw.kicad_sym",
    "ca-is3643hvw.kicad_mod",
    "ca-is3643hvw.glb",
    "ca-is3643hvw.step",
    "ca-is3643hvw.lbr",
    "docs/hero.png",
    "docs/ca-is3643hvw-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ca-is3643hvw-hero.glb",
    "ca-is3643hvw-hero.overlay.json",
    "ca-is3643hvw-etched.glb"
  ],
  "visibility": {
    "public": true
  }
}