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CA-IS3643HVW

Public Made by Adom

by adom

Chipanalog Digital Isolators (With Power), SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CA-IS3643HVW

Chipanalog · Digital Isolators (With Power) · SOIC-16-300mil

CA-IS3643HVW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in A-side supply that powers the internal DC-DC converter, recommended 3.15 V to 5.5 V (5 V typ), with 0.1 µF and 10 µF bypass capacitors placed within 2 mm of the pin.
2 GNDA power_in A-side ground reference for VDD, VDDL and the A-side logic pins.
3 VI1 input A-side logic input for channel 1 of the CA-IS3643; VIH minimum 2.0 V and VIL maximum 0.8 V.
4 VO2 output A-side logic output for channel 2 of the CA-IS3643, driving at most −4 mA high and 4 mA low at 5 V (−2 mA / 2 mA at 3.3 V).
5 VO3 output A-side logic output for channel 3 of the CA-IS3643, driving at most −4 mA high and 4 mA low at 5 V (−2 mA / 2 mA at 3.3 V).
6 VO4 output A-side logic output for channel 4 of the CA-IS3643, driving at most −4 mA high and 4 mA low at 5 V (−2 mA / 2 mA at 3.3 V).
7 VDDL power_in Logic supply for the A side (VW variant) that sets the A-side input threshold and output level, recommended 2.375 V to 5.5 V and may differ from VDD.
8 GNDA power_in A-side ground reference for VDD, VDDL and the A-side logic pins.
9 GNDB power_in B-side ground reference for VISO and the B-side logic pins.
10 SEL input VISO output-voltage select: tie to VISO for 5 V, tie to GNDB or leave open for 3.3 V, and do not change its level during start-up.
11 VI4 input B-side logic input for channel 4 of the CA-IS3643, with VIH minimum 2.0 V and VIL maximum 0.8 V.
12 VI3 input B-side logic input for channel 3 of the CA-IS3643, with VIH minimum 2.0 V and VIL maximum 0.8 V.
13 VI2 input B-side logic input for channel 2 of the CA-IS3643, with VIH minimum 2.0 V and VIL maximum 0.8 V.
14 VO1 output B-side logic output for channel 1 of the CA-IS3643, driving at most −4 mA high and 4 mA low at 5 V (−2 mA / 2 mA at 3.3 V).
15 GNDB power_in B-side ground reference for VISO and the B-side logic pins.
16 VISO power_out Isolated output supply of 5 V or 3.3 V set by SEL, with 0.1 µF and 10 µF bypass capacitors placed within 2 mm of the pin to GNDB; maximum load is 110 mA at 100 Mbps with a 5 V output at 25 °C and must be derated above 85 °C.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

CAD (KiCad official)

  • Symbol: CA-IS3643HVW
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ca-is3643hvw-etched.step / ca-is3643hvw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3643hvw.step / ca-is3643hvw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (39 pp, sha256 74e1e848c9ed7ac2, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF