component

CA-IS3642HW

Public Made by Adom

by adom

Chipanalog Pre-ordered Chips, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsca-is3642hwfactory-2.0.0extractor-text

Verified CA-IS3642HW

by Ray · last 12 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

12 Nov 2026RayPublished by the parts factory: tier lcsc, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CA-IS3642HW · SOIC-16-300mil · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 31-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-16W_7.5x10.3mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-b9fhdeto/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.28)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 33 kB, viewers/symbol.html 14 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ca-is3642hw.kicad_sym✓ ca-is3642hw.kicad_mod✓ ca-is3642hw.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers ca-is3642hw: viewers rendered from the public page · Ray
ca-is3642hw-etched.glb Publish 0.1.0 · Ray
ca-is3642hw-etched.step ca-is3642hw: factory component page (tier=lcsc) · Ray
ca-is3642hw-hero.glb ca-is3642hw: hero GLB from the etched model (keeps the MPN mark) · Ray
ca-is3642hw-hero.overlay.json ca-is3642hw: hero GLB from the etched model (keeps the MPN mark) · Ray
ca-is3642hw.glb Publish 0.1.0 · Ray
ca-is3642hw.kicad_mod Publish 0.1.0 · Ray
ca-is3642hw.kicad_sym Publish 0.1.0 · Ray
ca-is3642hw.lbr Publish 0.1.0 · Ray
ca-is3642hw.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 16 pins · Ray

CA-IS3642HW

Chipanalog · Pre-ordered Chips · SOIC-16-300mil

CA-IS3642HW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in A-side supply voltage, specified at 3 V to 5.5 V recommended with an absolute maximum of 6.0 V.
2 GNDA power_in A-side ground reference point.
3 VI1 input A-side logic input of forward channel 1 for CA-IS3642; VIH minimum 2.0 V and VIL maximum 0.8 V.
4 VI2 input A-side logic input of forward channel 2 for CA-IS3642; VIH minimum 2.0 V and VIL maximum 0.8 V.
5 VO3 output A-side logic output of reverse channel 3 for CA-IS3642 (data received from the B side).
6 VO4 output A-side logic output of reverse channel 4 for CA-IS3642 (data received from the B side).
7 NC unconnected No internal connection; it may float, be tied to VDD, or be tied to GND.
8 GNDA power_in A-side ground reference point.
9 GNDB power_in B-side ground reference point.
10 SEL input VISO output-voltage select: tie to VISO for 5 V, or to GNDB or leave floating for 3.3 V; the pin has a weak internal pull-down and a direct connection to GNDB is recommended in noisy systems.
11 VI4 input B-side logic input of reverse channel 4 for CA-IS3642; VIH minimum 2.0 V and VIL maximum 0.8 V.
12 VI3 input B-side logic input of reverse channel 3 for CA-IS3642; VIH minimum 2.0 V and VIL maximum 0.8 V.
13 VO2 output B-side logic output of forward channel 2 for CA-IS3642 (data received from the A side).
14 VO1 output B-side logic output of forward channel 1 for CA-IS3642 (data received from the A side).
15 GNDB power_in B-side ground reference point.
16 VISO power_out Isolated B-side output voltage, 5.0 V or 3.3 V as selected by the SEL pin, rated 5000 VRMS isolation.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16-300mil
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
电源电压 (VDD) recommended VDD 3 5.5 V 6
高电平输出电流 IOH IOH -4 mA VDDO1 = 5.0 V 6
高电平输出电流 IOH IOH -2 mA VDDO = 3.3 V 6
低电平输出电流 IOL IOL 4 mA VDDO = 5.0 V 6
低电平输出电流 IOL IOL 2 mA VDDO = 3.3 V 6
输入阈值逻辑高电平 VIH VIH 2 V 6
输入阈值逻辑低电平 VIL VIL 0.8 V 6
信号传输速率 DR DR 0 150 Mbps 6
环境温度 TA TA -40 25 125 °C 6
电源电压 VDD absolute VDD -0.5 6 V 6
隔离输出电压 VISO absolute VISO -0.5 6 V 6
输入电压 VIx, SEL, ENA Vin -0.5 V 6
输出电流 IO IO -20 20 mA 6
结温 TJ TJ 150 °C 6
存储温度 TSTG TSTG -65 150 °C 6
静电放电 人体模型 HBM VESD -6000 6000 V HBM, ANSI/ESDA/JEDEC JS-001, all pins 6
静电放电 充电器件模型 CDM VESD -2000 2000 V CDM, JEDEC JESD22-C101, all pins 6
最大功耗 PD PD 1 W VDD=5.5V, VISO=5V, load 130mA, all digital inputs 100Mbps 50% duty square wave, channel load 15pF 7
隔离输出电压 VISO (5V in, 5V out) VISO 4.75 5.07 5.43 V VDD=5V±10%, TA=-40 to 125°C, SEL shorted to VISO; external IISO = 0 to 50 mA 9
隔离输出电压 VISO (5V in, 5V out) VISO 4.5 5.07 5.43 V VDD=5V±10%, TA=-40 to 125°C, SEL shorted to VISO; external IISO = 0 to 130 mA 9
输出隔离电压纹波 峰峰值 (5V/5V) VISO(RIP) 60 mV VDD=5V±10%, SEL shorted to VISO 9
VISO 短路时电源电流 (5V/5V) ISCC_SC 42 mA VDD=5V±10%, VISO shorted to GNDB 9
VISO 输出带载电流 (5V/5V) IISO 120 mA VDD=5V±10%, SEL shorted to VISO 9
电源上升欠压保护阈值 VDD(UVLO+) (5V/5V) VDD(UVLO+) 2.6 2.9 V VDD=5V±10%, rising supply 9
电源下降欠压保护阈值 VDD(UVLO-) (5V/5V) VDD(UVLO-) 2 2.25 V VDD=5V±10%, falling supply 9
输入高电平漏电流 IIH (5V/5V) IIH 20 µA VIH = VDDI1 at VIx, Bx, ENx or SEL 9
输入低电平漏电流 IIL (5V/5V) IIL -20 µA VIL = 0 V at VIx, Bx, ENx or SEL 9
输出电压逻辑低电平 VOL (5V/5V) VOL 0.2 0.4 V IOL = 4 mA; Fig. 10-1 9
共模瞬变抗扰度 CMTI (5V/5V) CMTI 100 150 kV/µs VI = VDDI1 or 0 V, VCM = 1500 V; Fig. 10-2 9
隔离输出电压 VISO (5V in, 3.3V out) VISO 3.13 3.34 3.56 V VDD=5V±10%, TA=-40 to 125°C, SEL shorted to GNDB; external IISO = 0 to 50 mA 10
隔离输出电压 VISO (5V in, 3.3V out) VISO 3 3.34 3.56 V VDD=5V±10%, TA=-40 to 125°C, SEL shorted to GNDB; external IISO = 0 to 130 mA 10
输出隔离电压纹波 峰峰值 (5V/3.3V) VISO(RIP) 58 mV VDD=5V±10%, SEL shorted to GNDB 10
VISO 短路时电源电流 (5V/3.3V) ISCC_SC 38 mA VDD=5V±10%, VISO shorted to GNDB 10
VISO 输出带载电流 (5V/3.3V) IISO 110 mA VDD=5V±10%, SEL shorted to GNDB 10
电源上升欠压保护阈值 VDD(UVLO+) (5V/3.3V) VDD(UVLO+) 2.6 2.9 V VDD=5V±10%, rising supply 10
电源下降欠压保护阈值 VDD(UVLO-) (5V/3.3V) VDD(UVLO-) 2 2.25 V VDD=5V±10%, falling supply 10
输入高电平漏电流 IIH (5V/3.3V) IIH 20 µA VIH = VDDI1, VIx, EN, SEL pulled to VDDI 10
输入低电平漏电流 IIL (5V/3.3V) IIL -20 µA VIL = 0 V, VIx, EN, SEL pulled to 0 V 10
输出电压逻辑低电平 VOL (5V/3.3V) VOL 0.2 0.4 V IOL = 4 mA; Fig. 10-1 10
共模瞬变抗扰度 CMTI (5V/3.3V) CMTI 100 150 kV/µs VI = VDDI1 or 0 V, VCM = 1500 V; Fig. 10-2 10
隔离输出电压 VISO (3.3V in, 3.3V out) VISO 3.13 3.34 3.56 V VDD=3.3V±10%, TA=-40 to 125°C, SEL shorted to GNDB; external IISO = 0 to 50 mA 11
隔离输出电压 VISO (3.3V in, 3.3V out) VISO 3 3.34 3.56 V VDD=3.3V±10%, TA=-40 to 125°C, SEL shorted to GNDB; external IISO = 0 to 75 mA 11
输出隔离电压纹波 峰峰值 (3.3V/3.3V) VISO(RIP) 55 mV VDD=3.3V±10%, SEL shorted to GNDB 11
VISO 短路时电源电流 (3.3V/3.3V) ISCC_SC 32 mA VDD=3.3V±10%, VISO shorted to GNDB 11
VISO 输出带载电流 (3.3V/3.3V) IISO 70 mA VDD=3.3V±10%, SEL shorted to GNDB 11
输入高电平漏电流 IIH (3.3V/3.3V) IIH 20 µA VIH = VDDI1, VIx, EN, SEL pulled to VDDI 11
输入低电平漏电流 IIL (3.3V/3.3V) IIL -20 µA VIL = 0 V, VIx, EN, SEL pulled to 0 V 11
输出电压逻辑低电平 VOL (3.3V/3.3V) VOL 0.2 0.4 V IOL = 4 mA; Fig. 10-1 11
共模瞬变抗扰度 CMTI (3.3V/3.3V) CMTI 100 150 kV/µs VI = VDDI1 or 0 V, VCM = 1500 V; Fig. 10-2 11
最小脉冲宽度 PWminL (5V/5V) PWminL 5 ns VDD=5V±10%, TA=-40 to 125°C, SEL shorted to VISO 18
传播延迟 tPLH, tPHL (5V/5V) tPLH, tPHL 6 10 15 ns VDD=5V±10%, TA=-40 to 125°C; Fig. 10-1 18
脉冲宽度失真 PWD (5V/5V) PWD 0.2 4.5 ns /tPLH - tPHL/ 18
通道间输出偏移时间 trk(o) (5V/5V) trk(o) 0.4 2.5 ns Fig. 10-1 18
芯片间偏移时间 trk(pp) (5V/5V) trk(pp) 2 4.5 ns 18
输出上升时间 tr (5V/5V) tr 2.5 4 ns Fig. 10-1 18
输出下降时间 tf (5V/5V) tf 2.5 4 ns Fig. 10-1 18
结到环境热阻 RθJA (SOIC16-WB) RθJA 73.8 °C/W 7

CAD (KiCad official)

  • Symbol: CA-IS3642HW
  • Footprint: Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ca-is3642hw-etched.step / ca-is3642hw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3642hw.step / ca-is3642hw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (31 pp, sha256 426f9d6fab8911c4, retrieved 2026-11-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF