component
CA-IS2092VW
Public Made by Adomby adom
Chipanalog Isolated RS-485/422 Transceivers With Power, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "ca-is2092vw",
"version": "0.1.0",
"type": "component",
"description": "Chipanalog Isolated RS-485/422 Transceivers With Power, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"signal isolation devices",
"ca-is2092vw",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"ca-is2092vw.kicad_sym",
"ca-is2092vw.kicad_mod",
"ca-is2092vw.glb",
"ca-is2092vw.step",
"ca-is2092vw.lbr",
"docs/hero.png",
"docs/ca-is2092vw-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"ca-is2092vw-hero.glb",
"ca-is2092vw-hero.overlay.json"
],
"component": {
"mpn": "CA-IS2092VW",
"manufacturer": "Chipanalog",
"package": "SOIC-16-300mil",
"pin_count": 16,
"category": "Signal Isolation Devices",
"subcategory": "Isolated RS-485/422 Transceivers With Power",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590903641836363776",
"parts": {
"symbol": "ca-is2092vw.kicad_sym",
"footprint": "ca-is2092vw.kicad_mod",
"model_3d": "ca-is2092vw-hero.glb",
"model_3d_plain": "ca-is2092vw.glb",
"model_3d_step": "ca-is2092vw-etched.step",
"model_3d_step_plain": "ca-is2092vw.step",
"lbr": "ca-is2092vw.lbr"
},
"distributor_links": {
"lcsc": "C7422559"
},
"distributor_check": {
"checked_at": "2026-10-09T22:46:54Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "deferred",
"error": "shared DigiKey quota guard: 540 calls left today"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "VCC",
"type": "power_in",
"description": "Logic-side power input and DC-DC converter supply input, bypassed to GNDA with both 0.1µF and at least 10µF as close to the device as possible, with a recommended supply range of 3.15 V to 5.5 V."
},
{
"number": "2",
"name": "GNDA",
"type": "power_in",
"description": "Logic-side ground and the ground reference for the digital signals on the logic side."
},
{
"number": "3",
"name": "RO",
"type": "output",
"description": "Receiver data output: with RE low, RO is high when (VA − VB) > −20 mV and low when (VA − VB) < −200 mV, and it is high impedance when RE is high."
},
{
"number": "4",
"name": "RE",
"type": "input",
"description": "Receiver output enable: drive low or connect to GNDA to enable the receiver, and drive high to disable it, which puts RO in high impedance."
},
{
"number": "5",
"name": "DE",
"type": "input",
"description": "Driver output enable: drive high to enable the bus driver outputs and drive low or connect to GNDA to disable them, with an internal weak pull-down to GNDA."
},
{
"number": "6",
"name": "DI",
"type": "input",
"description": "Driver input: with DE high, a logic low forces the non-inverting output A low and the inverting output B high, and a logic high forces A high and B low."
},
{
"number": "7",
"name": "VCCL",
"type": "power_in",
"description": "Logic-supply input for the logic-side input/output, bypassed to GNDA with a 1µF capacitor, with a recommended supply range of 2.375 V to 5.5 V (see review note on the +2.7 V figure in the footnote)."
},
{
"number": "8",
"name": "GNDA",
"type": "power_in",
"description": "Logic-side ground and the ground reference for the digital signals on the logic side."
},
{
"number": "9",
"name": "GNDB",
"type": "power_in",
"description": "Cable-side ground and the ground reference for the RS-485/RS-422 bus signals."
},
{
"number": "10",
"name": "SEL",
"type": "input",
"description": "VISO select: shorted to VISO sets VISO to 5.0 V, while shorted to GNDB or left floating sets VISO to 3.3 V, and VISO must not exceed VCC (so with VCC = 3.3 V, SEL must be floating or tied to GNDB)."
},
{
"number": "11",
"name": "NC",
"type": "unconnected",
"description": "No internal connection on the cable side."
},
{
"number": "12",
"name": "A",
"type": "bidirectional",
"description": "Non-inverting RS-485/RS-422 receiver input and driver output on the bus."
},
{
"number": "13",
"name": "B",
"type": "bidirectional",
"description": "Inverting RS-485/RS-422 receiver input and driver output on the bus."
},
{
"number": "14",
"name": "VISOIN",
"type": "power_in",
"description": "Cable-side power supply input, bypassed to GNDB with at least 1µF as close to the device as possible."
},
{
"number": "15",
"name": "GNDB",
"type": "power_in",
"description": "Cable-side ground and the ground reference for the RS-485/RS-422 bus signals."
},
{
"number": "16",
"name": "VISO",
"type": "power_out",
"description": "Isolated DC-DC power output for the cable side, bypassed to GNDB with both 0.1µF and at least 10µF as close to the device as possible, with VISO selected as 3.3 V or 5.0 V via SEL."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Package hint says SOIC-16-300mil, but the datasheet lists only SOIC16-WB(W), a wide-body 16-pin SOIC; Pin 7 (VCCL) supply range conflicts within the datasheet: the footnote to Table 6-1 says +2.7 V to +; Pin 10 (SEL) is labelled 'Digital I/O' in the datasheet but functions as a strap that selects VISO; "
],
"pages_sent": 6,
"cost_usd": 0.0555,
"at": "2026-10-09T22:44:41"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590903641836363776",
"pages": 27,
"sha256": "8a16f8532f94d2de",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ca-is2092vw.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.0,
9.9,
1.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
"checked": "2026-10-09",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ca-is2092vw-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.0,
9.9,
1.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "4535e67574081e5f52d51e71863e1bcc37e48bed1c06ee6acb7930cb155c27ed",
"checked": "2026-10-09",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}