component
CA-IS2092VW
Public Made by Adomby adom
Chipanalog Isolated RS-485/422 Transceivers With Power, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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CA-IS2092VW
Chipanalog · Isolated RS-485/422 Transceivers With Power · SOIC-16-300mil
CA-IS2092VW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Logic-side power input and DC-DC converter supply input, bypassed to GNDA with both 0.1µF and at least 10µF as close to the device as possible, with a recommended supply range of 3.15 V to 5.5 V. |
| 2 | GNDA | power_in | Logic-side ground and the ground reference for the digital signals on the logic side. |
| 3 | RO | output | Receiver data output: with RE low, RO is high when (VA − VB) > −20 mV and low when (VA − VB) < −200 mV, and it is high impedance when RE is high. |
| 4 | RE | input | Receiver output enable: drive low or connect to GNDA to enable the receiver, and drive high to disable it, which puts RO in high impedance. |
| 5 | DE | input | Driver output enable: drive high to enable the bus driver outputs and drive low or connect to GNDA to disable them, with an internal weak pull-down to GNDA. |
| 6 | DI | input | Driver input: with DE high, a logic low forces the non-inverting output A low and the inverting output B high, and a logic high forces A high and B low. |
| 7 | VCCL | power_in | Logic-supply input for the logic-side input/output, bypassed to GNDA with a 1µF capacitor, with a recommended supply range of 2.375 V to 5.5 V (see review note on the +2.7 V figure in the footnote). |
| 8 | GNDA | power_in | Logic-side ground and the ground reference for the digital signals on the logic side. |
| 9 | GNDB | power_in | Cable-side ground and the ground reference for the RS-485/RS-422 bus signals. |
| 10 | SEL | input | VISO select: shorted to VISO sets VISO to 5.0 V, while shorted to GNDB or left floating sets VISO to 3.3 V, and VISO must not exceed VCC (so with VCC = 3.3 V, SEL must be floating or tied to GNDB). |
| 11 | NC | unconnected | No internal connection on the cable side. |
| 12 | A | bidirectional | Non-inverting RS-485/RS-422 receiver input and driver output on the bus. |
| 13 | B | bidirectional | Inverting RS-485/RS-422 receiver input and driver output on the bus. |
| 14 | VISOIN | power_in | Cable-side power supply input, bypassed to GNDB with at least 1µF as close to the device as possible. |
| 15 | GNDB | power_in | Cable-side ground and the ground reference for the RS-485/RS-422 bus signals. |
| 16 | VISO | power_out | Isolated DC-DC power output for the cable side, bypassed to GNDB with both 0.1µF and at least 10µF as close to the device as possible, with VISO selected as 3.3 V or 5.0 V via SEL. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CA-IS2092VW - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
ca-is2092vw-etched.step/ca-is2092vw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is2092vw.step/ca-is2092vw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (27 pp, sha256
8a16f8532f94d2de, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).