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BQ40Z60RHBR

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Texas Instruments Battery Management ICs, VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower supply chipbq40z60rhbrfactory-2.0.0extractor-text

Verified BQ40Z60RHBR

by Ray · last 2 Nov 2026 · 1 record · files match
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Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: BQ40Z60RHBR · VQFN-32(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 46-page datasheet
  • ✓distributor: lcsc C3681640, digikey BQ40Z60RHBR-ND, mouser 595-BQ40Z60RHBR
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-zkdl5p1t/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.43)
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ bq40z60rhbr.kicad_sym✓ bq40z60rhbr.kicad_mod✓ bq40z60rhbr.step
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BQ40Z60RHBR

Texas Instruments · Battery Management ICs · VQFN-32(5x5)

BQ40Z60RHBR from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BAT power_in Battery input pin and primary power supply (2.2 V to 26 V recommended, absolute maximum 30 V).
2 PBI power_in Power supply backup input pin (2.2 V to 26 V recommended, absolute maximum 30 V).
3 VC4 input Sense voltage input for the most positive cell, balance current input for that cell, and battery stack measurement input.
4 VC3 input Sense voltage input for the third most positive cell, balance current input for that cell, and return balance current for the most positive cell.
5 VC2 input Sense voltage input for the second most positive cell, balance current input for that cell, and return balance current for the most positive cell.
6 VC1 input Sense voltage input for the least positive cell, balance current input for that cell, and return balance current for the second most positive cell.
7 SRN input Analog input to the internal coulomb counter for integrating the small voltage between SRP and SRN (absolute maximum -0.3 V to 0.3 V).
8 SRP input Analog input to the internal coulomb counter for integrating the small voltage between SRP and SRN, where SRP is the top of the sense resistor (absolute maximum -0.3 V to 0.3 V).
9 VSS power_in Device ground.
10 TS1 input Thermistor input for temperature sensor channel 1 (absolute maximum -0.3 V to VREG + 0.3 V).
11 TS2 input Thermistor input for temperature sensor channel 2 (absolute maximum -0.3 V to VREG + 0.3 V).
12 TS3 input Thermistor input for temperature sensor channel 3 (absolute maximum -0.3 V to VREG + 0.3 V).
13 TS4 input Thermistor input for temperature sensor channel 4 (absolute maximum -0.3 V to VREG + 0.3 V).
14 GPIO0 bidirectional Multi-function open-drain I/O (absolute maximum 30 V); see IO Configuration in the bq40z60 Technical Reference Manual (SLUUA04).
15 GPIO1 bidirectional Multi-function open-drain I/O (absolute maximum 30 V); see IO Configuration in the bq40z60 Technical Reference Manual (SLUUA04).
16 SMBD bidirectional SMBus data pin, open-drain input/output (absolute maximum 30 V).
17 SMBC bidirectional SMBus clock pin, open-drain input/output (absolute maximum 30 V).
18 VFB input Feedback sense input for the charger control loop (absolute maximum 16 V).
19 HSRN input High sense resistor negative node input (absolute maximum 30 V).
20 HSRP input High sense resistor positive node input (absolute maximum 30 V).
21 AFEFUSE output Fuse drive output pin (absolute maximum 30 V).
22 VCC power_in Power supply input (2.2 V to 26 V recommended, absolute maximum 30 V).
23 REGN power_out Charger FET gate drive regulator output (0 V to 6.5 V recommended, absolute maximum 7 V).
24 PGND power_in Power ground.
25 LODRV output Low-side charging FET gate control output (absolute maximum 7 V).
26 PH bidirectional Charger phase signal input (absolute maximum 32 V).
27 HIDRV output High-side charging FET gate control output (absolute maximum 36 V).
28 BTST input High-side bootstrap capacitor input (0 V to 35 V recommended, absolute maximum 36 V).
29 ACFET output AC FET gate control output (0 V to 35 V recommended, absolute maximum 36 V).
30 DSG output N-channel discharge FET drive output pin (absolute maximum 32 V).
31 ACP input Adapter input pin (absolute maximum 30 V).
32 CHG output N-channel charge FET drive output pin (absolute maximum 32 V).
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32(5x5)
Category Power Supply Chip
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage BAT, VCC, PBI (abs max) VSupply -0.3 30 V BAT, VCC, PBI 5
Supply voltage REGN (abs max) VSupply -0.3 7 V REGN 5
Input voltage ACP, SMBC, SMBD, GPIO0, GPIO1 (abs max) VIN -0.3 30 V 5
Input voltage SRP, SRN (abs max) VIN -0.3 0.3 V 5
Input voltage HSRP, HSRN (abs max) VIN -0.3 30 V 5
Input voltage PH (abs max) VIN -0.3 32 V 5
Input voltage VFB (abs max) VIN -0.3 16 V 5
Output voltage CHG, DSG (abs max) VO -0.3 32 V 5
Output voltage HIDRV, BTST, ACFET (abs max) VO -0.3 36 V 5
Output voltage LODRV (abs max) VO -0.3 7 V 5
Output voltage AFEFUSE (abs max) VO -0.3 30 V 5
Maximum VSS current ISS 50 mA 5
Functional temperature TFUNC -40 110 °C 5
ESD HBM V(ESD) -2000 2000 V HBM 5
ESD CDM V(ESD) -500 500 V CDM 5
Supply voltage BAT, VCC, PBI VSupply 2.2 26 V BAT, VCC, PBI 5
Supply voltage ACFET, BTST VSupply 0 35 V ACFET, BTST 5
Supply voltage REGN VSupply 0 6.5 V REGN 5
Shutdown voltage VSHUTDOWN- 1.8 2 2.2 V VACP < VSHUTDOWN- 5
Start-up voltage VSHUTDOWN+ 2.05 2.25 2.45 V VACP > VSHUTDOWN- + VHYS 5
Shutdown voltage hysteresis VHYS 250 mV VSHUTDOWN+, VSHUTDOWN- 5
Input voltage SRP, SRN VIN -0.2 0.2 V 6
Input voltage HSRP, HSRN VIN -0.5 0.5 V 6
Input voltage VFB VIN 0 14 V 6
Output voltage LODRV VO 0 6.5 V 6
External PBI capacitor CPBI 2.2 µF 6
Operating temperature TOPR -40 85 °C 6
Junction-to-ambient thermal resistance, High K RθJA 36 °C/W RHB (VQFN) 32 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 31.5 °C/W 6
Junction-to-board thermal resistance RθJB 8 °C/W 6
Junction-to-top characterization parameter ψJT 0.5 °C/W 6
Junction-to-board characterization parameter ψJB 7.9 °C/W 6
Junction-to-case (bottom) thermal resistance RθJCbot 2.2 °C/W 6
VCC operating range, charger enabled VCC 4 25 V Operation with charger enabled 6
VCC operating range, charger disabled VCC 2.5 25 V Operation with charger disabled 6
Undervoltage lock out VCC-UV 2.2 2.45 V VCC falling 6
NORMAL mode current, charger enabled INORMAL 1250 1850 µA CPU = ACTIVE, Charger Enabled, No Communication 7
NORMAL mode current, charger disabled INORMAL 310 445 µA CPU = HALT, Charger Disabled, No Communication 7
SLEEP mode current, HFO ON, CHG/DSG ON ISLEEP 122 183 µA CPU = HALT, HFO = ON, CHG = ON, DSG = ON 7
SLEEP mode current, HFO OFF, CHG/DSG ON ISLEEP 92 138 µA CPU = HALT, HFO = OFF, CHG = ON, DSG = ON 7
SLEEP mode current, HFO ON, CHG/DSG OFF ISLEEP 82 128 µA CPU = HALT, HFO = ON, CHG = OFF, DSG = OFF 7
SLEEP mode current, HFO OFF, CHG/DSG OFF ISLEEP 52 83 µA CPU = HALT, HFO = OFF, CHG = OFF, DSG = OFF 7
SHUTDOWN mode current ISHUTDOWN 0.5 2 µA CPU = HALT, HFO = OFF, LFO = OFF, REG18 = OFF, Charger Disabled, No Communication 7
BAT to VCC switchover voltage VSWITCHOVER- 2 2.1 2.2 V VBAT < VSWITCHOVER- 7
VCC to BAT switchover voltage VSWITCHOVER+ 3 3.1 3.2 V VBAT > VSWITCHOVER- + VHYS 7
Switchover voltage hysteresis VHYS 1000 mV VSWITCHOVER+, VSWITCHOVER- 7
Input leakage current, BAT pin ILKG 1 µA BAT = 0 V, VCC = 25 V 7
Input leakage current, VCC pin ILKG 1 µA BAT = 25 V, VCC = 0 V 7
Input leakage current, BAT and VCC pins ILKG 1 µA BAT = 0 V, VCC = 0 V, PBI = 25 V 7
Internal pulldown resistance ACP RPD 30 40 50 kΩ ACP 7
SMBus input voltage high VIH 1.3 V SMBC, SMBD, VREG = 1.8 V 17
SMBus input voltage low VIL 0.8 V SMBC, SMBD, VREG = 1.8 V 17
SMBus output low voltage VOL 0.4 V SMBC, SMBD, VREG = 1.8 V, IOL = 1.5 mA 17
SMBus input capacitance CIN 5 pF 17
SMBus input leakage current ILKG 1 µA 17
SMBus pulldown resistance RPD 0.7 1 1.3 MΩ 17
SMBus operating frequency fSMB 10 100 kHz SLAVE mode, SMBC 50% duty cycle 17
SMBus XL operating frequency fSMBXL 40 400 kHz SLAVE mode 17
OCD detection delay time tOCD 1 31 ms 18
SCC detection delay time tSCC 0 915 µs 18
Current fault delay time accuracy tACC -10 10 % Max delay setting 18

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper 3. Place the inductor input pin as close as possible to the switching MOSFET output pin. Minimize the copper 34

CAD (KiCad official)

  • Symbol: BQ40Z60RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: bq40z60rhbr-etched.step / bq40z60rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq40z60rhbr.step / bq40z60rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 f6cbeec32ec982dc, retrieved 2026-11-02, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF