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BLUENRG-345MC

Public Made by Adom

by adom

STMicroelectronics RF Transceiver ICs, QFN-48-EP(6x6). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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BLUENRG-345MC

STMicroelectronics · RF Transceiver ICs · QFN-48-EP(6x6)

BLUENRG-345MC from STMicroelectronics, in a QFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB3 bidirectional 5 V tolerant FT_a I/O with analog switch function; alternate functions USART_CTS, LPUART_TX, TIM1_CH4, additional functions ADC_VINP0 and wakeup.
2 PB2 bidirectional 5 V tolerant FT_a I/O with analog switch function; alternate functions USART_RTS_DE, PDM_DATA, TIM1_CH3, additional functions ADC_VINM0 and wakeup.
3 PB1 bidirectional 5 V tolerant FT_a I/O with analog switch function; alternate functions SPI1_NSS, PDM_CLK, TIM1_ETR, additional functions ADC_VINP1 and wakeup.
4 PB0 bidirectional 5 V tolerant FT_a I/O with analog switch function; alternate functions USART_RX, LPUART_RTS_DE, TIM1_CH2N, additional functions ADC_VINM1 and wakeup.
5 PA15 bidirectional 5 V tolerant FT_a I/O with analog switch function; alternate functions I2C2_SMBA, SPI1_MOSI, TIM1_BKIN2, additional functions ADC_VINP2 and wakeup.
6 PA14 bidirectional 5 V tolerant FT_a I/O with analog switch function; alternate functions I2C2_SDA, SPI1_MISO, TIM1_BKIN, additional functions ADC_VINM2 and wakeup.
7 PA13 bidirectional 5 V tolerant FT_a I/O with analog switch function; alternate functions I2C2_SCL, SPI1_SCK, SPI2_MISO, TIM1_ETR, I2S2_MISO, additional functions ADC_VINP3 and wakeup.
8 PA12 bidirectional 5 V tolerant FT_a I/O with analog switch function; alternate functions I2C1_SMBA, SPI1_NSS, SPI2_MOSI, TIM1_CH1, I2S2_SD, additional functions ADC_VINM3 and wakeup.
9 PA11 bidirectional 5 V tolerant FT I/O; alternate functions MCO, SPI1_NSS, RX_SEQUENCE, SPI3_MOSI, TIM1_CH6, I2S3_SD; additional functions wakeup, GPIO in DEEPSTOP and RTC_OUT.
10 PA10 bidirectional 5 V tolerant FT I/O; alternate functions LCO, SPI1_MISO, TX_SEQUENCE, SPI3_MCK, TIM1_CH5, I2S3_MCK; additional functions BOOT, wakeup, GPIO in DEEPSTOP and LCO.
11 PA9 bidirectional 5 V tolerant FT I/O; alternate functions USART_TX, SPI1_SCK, RTC_OUT, SPI3_NSS, TIM1_CH4, I2S3_WS; additional functions wakeup, GPIO in DEEPSTOP and LCO.
12 PA8 bidirectional 5 V tolerant FT I/O; alternate functions USART_RX, SPI1_MOSI, RX_SEQUENCE, SPI3_MISO, TIM1_CH3, I2S3_MISO; additional functions wakeup, GPIO in DEEPSTOP and RTC_OUT.
13 PA0 bidirectional 5 V tolerant FT_f I/O (Fm+ capable); alternate functions I2C1_SCL, USART_CTS, SPI2_MCK, TIM1_CH3, I2S2_MCK; additional function wakeup.
14 PA1 bidirectional 5 V tolerant FT_f I/O (Fm+ capable); alternate functions I2C1_SDA, SPI2_MISO, USART_TX, TIM1_CH4, I2S2_MISO; additional function wakeup.
15 PA2 bidirectional 5 V tolerant FT I/O; alternate functions SWDIO, USART_CK, TIM_BKIN, SPI3_MCK, TIM1_CH5, I2S3_MCK; additional function wakeup.
16 PA3 bidirectional 5 V tolerant FT I/O; alternate functions SWCLK, USART_RTS_DE, TIM_BKIN2, SPI3_SCK, TIM1_CH6, I2S3_SCK; additional function wakeup.
17 PA4 bidirectional 5 V tolerant FT I/O; alternate functions LCO, SPI2_NSS, LPUART_TX, TIM1_CH1, I2S2_WS; additional functions wakeup, GPIO in DEEPSTOP and LCO.
18 PA5 bidirectional 5 V tolerant FT I/O; alternate functions MCO, SPI2_SCK, LPUART_RX, TIM1_CH2, I2S2_SCK; additional functions wakeup, GPIO in DEEPSTOP and LCO.
19 PA6 bidirectional 5 V tolerant FT I/O; alternate functions LPUART_CTS, SPI2_MOSI, SPI2_NSS, TIM1_CH1, I2S2_SD, I2S2_WS; additional functions wakeup, GPIO in DEEPSTOP and LCO.
20 PA7 bidirectional 5 V tolerant FT I/O; alternate functions LPUART_RTS_DE, SPI2_MISO, SPI2_SCK, TIM1_CH2, I2S2_MISO, I2S2_SCK; additional functions wakeup, GPIO in DEEPSTOP and RTC_OUT.
21 VDD2 power_in Battery voltage input, 1.7 to 3.6 V.
22 RF1 bidirectional RF input/output with 50 Ω impedance.
23 VDDRF power_in Battery voltage input, 1.7 to 3.6 V.
24 OSCOUT bidirectional RF pin for the 32 MHz crystal connection.
25 OSCIN bidirectional RF pin for the 32 MHz crystal connection.
26 VDD4 power_in Battery voltage input, 1.7 to 3.6 V.
27 PB15 bidirectional 5 V tolerant FT I/O; alternate functions I2C1_SMBA, TX_SEQUENCE, MCO, TIM1_CH4N, TIM1_CH6, USART_TX.
28 PB14 bidirectional 5 V tolerant FT_a I/O with analog switch function; alternate functions SPI1_MOSI, I2C2_SDA, TIM1_ETR, TIM1_CH3N, TIM1_CH5, USART_RX; additional function VIN_PVD.
29 PB13 bidirectional 5 V tolerant FT I/O; alternate functions SPI1_MISO, I2C2_SCL, PDM_CLK, TIM1_BKIN2, TIM1_CH4; additional function SXTAL1.
30 PB12 bidirectional 5 V tolerant FT I/O; alternate functions SPI1_SCK, LCO, PDM_DATA, TIM1_BKIN, TIM1_CH3; additional function SXTAL0.
31 VCAP power_out 1.2 V digital core supply pin.
32 VFBSD power_out SMPS output pin.
33 NC unconnected Not connected; the datasheet gives no function for this pin.
34 VSSSD power_in SMPS ground pin.
35 VLXSD passive SMPS input/output pin.
36 VDDSD power_in Battery voltage input, 1.7 to 3.6 V.
37 VDD3 power_in Battery voltage input, 1.7 to 3.6 V.
38 RSTN bidirectional Bidirectional reset pin with weak pull-up resistor.
39 VDD1 power_in Battery voltage input, 1.7 to 3.6 V.
40 VDDA power_out 1.2 V analog ADC core supply pin.
41 PB11 bidirectional 5 V tolerant FT I/O; alternate functions SPI1_SCK, SPI2_NSS, I2C1_SCL, TIM1_CH1, TIM1_CH4N, I2S2_WS; additional function wakeup.
42 PB10 bidirectional 5 V tolerant FT I/O; alternate functions SPI1_NSS, SPI2_SCK, I2C1_SDA, TIM1_CH2, TIM1_CH3N, I2S2_SCK; additional function wakeup.
43 PB9 bidirectional 5 V tolerant FT I/O; alternate functions USART_TX, LPUART_CTS, SPI2_MCK, TIM1_CH1N, TIM1_CH2N, I2S2_MCK; additional function wakeup.
44 PB8 bidirectional 5 V tolerant FT I/O; alternate functions USART_CK, LPUART_RX, TIM1_CH4, TIM1_CH1N; additional function wakeup.
45 PB7 bidirectional 5 V tolerant FT_f I/O (Fm+ capable); alternate functions I2C2_SDA, SPI2_SCK, LPUART_RX, TIM1_CH2, I2S2_SCK; additional function wakeup.
46 PB6 bidirectional 5 V tolerant FT_f I/O (Fm+ capable); alternate functions I2C2_SCL, SPI2_NSS, LPUART_TX, TIM1_CH1, I2S2_WS; additional function wakeup.
47 PB5 bidirectional 3.6 V tolerant TT I/O, not 5 V tolerant; alternate functions LPUART_RX, SPI2_MOSI, PDM_CLK, I2S2_SD; additional functions PGA_VBIAS_MIC and wakeup.
48 PB4 bidirectional 5 V tolerant FT I/O; alternate functions LPUART_TX, SPI2_MISO, PDM_DATA, I2S2_MISO; additional functions PGA_VIN and wakeup.
EP GND power_in Exposed pad; ground.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package QFN-48-EP(6x6)
Category RF And Wireless
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC-DC converter supply voltage input and output VDD1, VDD2, VDD3, VDD4, VDDRF, VDDSD -0.3 3.9 V 35
DC voltage on linear voltage regulator VCAP, VDDA -0.3 1.32 V 35
DC voltage on HSE FXTALOUT, FXTALIN -0.3 1.32 V 35
DC voltage on digital input/output pins PA0 to PA15, PB0 to PB4, PB6 to PB15 -0.3 3.9 V 35
DC voltage on XTAL pins and PGA_VBIAS_MIC XTAL0/PB12, XTAL1/PB13, PB5 -0.3 3.6 V 35
DC voltage on RF pin RF1 1.4 V 35
Variations between different VDDX power pins of the same domain /ΔVDD/ 50 mV 35
Total current into sum of all VDD power lines (source) ΣIVDD 130 mA 35
Total current out of sum of all ground lines (sink) ΣIVGND 130 mA 35
Maximum current into each VDD power pin (source) IVDD(PIN) 100 mA 35
Maximum current out of each ground pin (sink) IVGND(PIN) 100 mA 35
Output current sunk by any I/O and control pin IIO(PIN) 20 mA sunk 35
Output current sourced by any I/O and control pin IIO(PIN) 20 mA sourced 35
Total output current sunk by sum of all I/Os and control pins ΣIIO(PIN) 100 mA sunk 35
Total output current sourced by sum of all I/Os and control pins ΣIIO(PIN) 100 mA sourced 35
Storage temperature range TSTG -125 -40 °C 35
Maximum junction temperature TJ 125 °C 35
Internal AHB clock frequency fHCLK 1 64 MHz 39
Internal APB0 clock fPCLK0 1 64 MHz 39
Internal APB1 clock frequency fPCLK1 1 64 MHz 39
Internal APB2 clock frequency fPCLK2 16 32 MHz 39
Standard operating voltage VDD 1.7 3.6 V 39
SMPS feedback voltage VFBSMPS 1.4 3.6 V 39
Minimum RF voltage VDDRF 1.7 3.6 V 39
I/O input voltage VIN -0.3 V Printed maximum is VDD+0.3 39
Power dissipation PD 30 mW TA=105 °C, QFN48 package 39
Ambient temperature TA -40 105 °C Maximum power dissipation 39
Junction temperature range TJ -40 105 °C 39
Frequency range FRANGE 2400 2483.5 MHz 40
RF channel center frequency RFCH 2402 2480 MHz 40
Frequency deviation average Δf1 450 550 kHz 40
Center frequency deviation CFdev -150 150 kHz During the packet and including both initial frequency offset and drift 40
Modulation index Mindex 0.45 0.5 0.55 40
Maximum output PMAX 8 dBm At antenna connector, VSMPS = 1.9 V, LDO code 40
Minimum output PMIN -20 dBm At antenna connector 40
RF power accuracy PRFC -1.5 1.5 dB @ 27 °C 40
Symbol time accuracy STacc -50 50 ppm 40
On-air data rate Rgfsk 1 2 Mbps 40
32-bit programming time tprog 20 40 µs 49
Page (2 kbyte) erase time tERASE 20 40 ms 49
Mass erase time tME 20 40 ms 49
Endurance NEND 10 kcycles TA = -40 to +105 ºC 49
Data retention tRET 10 Years TA = 105 ºC 49
Electrostatic discharge voltage (human body model) VESD(HBM) 2000 V Conforming to ANSI/ESDA/JEDEC JS-001 49
Electrostatic discharge voltage (charge device model) VESD(CBM) 500 V Conforming to ANSI/ESDA/STM5.3.1 JS-002 C2a 49
Input leakage current Ilkg -100 100 nA 0 <= VIN <= Max(VDDx) 49
Input leakage current Ilkg 650 nA Max(VDDx) <= VIN <= Max(VDDx) +1 V 49
Input leakage current Ilkg 200 nA Max(VDDx) + 1 V < VIN <= 5.5 V 49
Pull-up resistor RPU 25 40 55 kΩ VIN = GND 49
Pull-down resistor RPD 25 40 55 kΩ VIN = VDD 50
Output low level voltage for I/O pin, CMOS port VOL 0.4 V /IIO/ = 8 mA, VDD ≥ 2.7 V 50
Output low level voltage for I/O pin VOL 1.3 V /IIO/ = 20 mA, VDD ≥ 2.7 V 50
Output low level voltage for I/O pin VOL 0.4 V /IIO/ = 4 mA, VDD ≥ 1.62 V 50
Weak pull-up equivalent resistor (RSTN) RPU 25 40 55 kΩ VIN=GND 50
Analog supply voltage VDDA 1.2 1.32 V 51
Differential non-linearity DNL -0.7 0.7 LSB 51
Integral non-linearity INL -1 1 LSB 51
Error in temperature TrERR -4 4 °C 52
Maximum pulse width of spikes suppressed by the analog filter tAF 50 110 ns 54
Thermal resistance junction-ambient ΘJA 25.1 °C/W QFN48, 6 mm x 6 mm 65

CAD (KiCad official)

  • Symbol: BLUENRG-345MC
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: QFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: bluenrg-345mc-etched.step / bluenrg-345mc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bluenrg-345mc.step / bluenrg-345mc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (73 pp, sha256 c3c8def9f2699f65, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF