component
BD9P155EFV-CE2
Public Made by Adomby adom
ROHM Semicon DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
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"version": "0.1.0",
"type": "component",
"description": "ROHM Semicon DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"power management ics",
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"component": {
"mpn": "BD9P155EFV-CE2",
"manufacturer": "ROHM Semicon",
"package": "HTSSOP-20-EP",
"pin_count": 21,
"category": "Power Management ICs",
"subcategory": "DC-DC Converters",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/705bc1aac3f4c1501284972a60bfdcd3.pdf",
"parts": {
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"lbr": "bd9p155efv-ce2.lbr"
},
"distributor_links": {
"lcsc": "C1518750",
"digikey": "846-BD9P155EFV-CE2TR-ND",
"mouser": "755-BD9P155EFV-CE2"
},
"distributor_check": {
"checked_at": "2026-11-02T17:31:02Z",
"source": "Component Ocean /api/assign-pns",
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"status": "found"
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"status": "found"
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},
"pins": [
{
"number": "1",
"name": "EN",
"type": "input",
"description": "Enable pin: low level of 0.8 V or lower disables the device and high level of 2.0 V or higher enables it, and it must not be left open."
},
{
"number": "2",
"name": "VIN",
"type": "power_in",
"description": "Power supply input for the internal circuit, to be connected to the PVIN pins."
},
{
"number": "3",
"name": "PVIN",
"type": "power_in",
"description": "Power supply input for the switching regulator output stage, with input ceramic capacitors connected between PGND and these pins."
},
{
"number": "4",
"name": "PVIN",
"type": "power_in",
"description": "Power supply input for the switching regulator output stage, with input ceramic capacitors connected between PGND and these pins."
},
{
"number": "5",
"name": "N.C.",
"type": "unconnected",
"description": "Not connected to the chip; leave open, and confirm no problem if adjacent pins may be shorted in the application."
},
{
"number": "6",
"name": "PGND",
"type": "power_in",
"description": "Ground pin for the switching regulator output stage."
},
{
"number": "7",
"name": "PGND",
"type": "power_in",
"description": "Ground pin for the switching regulator output stage."
},
{
"number": "8",
"name": "SW",
"type": "output",
"description": "Switching node connected to the source of the internal high-side FET and the drain of the internal low-side FET, used for the power inductor and bootstrap capacitor."
},
{
"number": "9",
"name": "SW",
"type": "output",
"description": "Switching node connected to the source of the internal high-side FET and the drain of the internal low-side FET, used for the power inductor and bootstrap capacitor."
},
{
"number": "10",
"name": "BST",
"type": "passive",
"description": "Connect a 0.1 µF (Typ) bootstrap capacitor between this pin and the SW pins, which supplies the high-side FET gate drive."
},
{
"number": "11",
"name": "OCP_SEL",
"type": "input",
"description": "Overcurrent threshold select: high (connected to VREG) sets 1.250 A (Typ) and low (connected to GND) sets 0.625 A (Typ) as the average inductor current limit."
},
{
"number": "12",
"name": "MODE",
"type": "input",
"description": "Mode select: high for forced PWM, low or open for AUTO (PWM/LLM), or a applied clock for SYNC mode."
},
{
"number": "13",
"name": "SSCG",
"type": "input",
"description": "Spread spectrum select: high (connected to VREG) enables spread spectrum and low (connected to GND) disables it."
},
{
"number": "14",
"name": "RESET",
"type": "output",
"description": "Open-drain output reset pin that requires a pull-up resistor to VREG or a supply within the RESET pin absolute maximum rating, with 5 kΩ to 100 kΩ recommended."
},
{
"number": "15",
"name": "GND",
"type": "power_in",
"description": "Ground pin for the device."
},
{
"number": "16",
"name": "VOUT_DIS",
"type": "input",
"description": "Discharges the VOUT node when connected to VOUT, and must be connected to GND when the discharge function is not required."
},
{
"number": "17",
"name": "VOUT_SNS",
"type": "input",
"description": "Inverting input of GmAmp1 used for OVP, SCP and RESET detection and for clamp and phase compensation; connect to the output voltage."
},
{
"number": "18",
"name": "N.C.",
"type": "unconnected",
"description": "Not connected to the chip for the BD9P155EFV-C; leave open, and confirm no problem if adjacent pins may be shorted in the application."
},
{
"number": "19",
"name": "VCC_EX",
"type": "power_in",
"description": "Power supply input for the internal circuit that supplies VREG when voltage between 3.2 V (VTEXH, Max) and 5.65 V (VEXOVPL, Min) is applied, and must be connected to GND if unused."
},
{
"number": "20",
"name": "VREG",
"type": "power_out",
"description": "Outputs 3.3 V (Typ) for the internal circuit, requires a 1.0 µF (Typ) ceramic capacitor, and must not drive external loads other than the OCP_SEL, MODE and SSCG pins and the RESET pull-up."
},
{
"number": "21",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet names the package HTSSOP-B20 (6.5 mm x 6.4 mm x 1.0 mm), not HTSSOP-20-EP as in the pa; The exposed pad (EXP-PAD) is printed without a number, so it is not listed as a numbered pin. It con"
],
"pages_sent": 13,
"cost_usd": 0.0244,
"at": "2026-11-02T17:30:53"
},
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/705bc1aac3f4c1501284972a60bfdcd3.pdf",
"pages": 60,
"sha256": "f5977b9e0766c210",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 21,
"described": 21,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
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}