component
BD9P155EFV-CE2
Public Made by Adomby adom
ROHM Semicon DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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BD9P155EFV-CE2
ROHM Semicon · DC-DC Converters · HTSSOP-20-EP
BD9P155EFV-CE2 from ROHM Semicon, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable pin: low level of 0.8 V or lower disables the device and high level of 2.0 V or higher enables it, and it must not be left open. |
| 2 | VIN | power_in | Power supply input for the internal circuit, to be connected to the PVIN pins. |
| 3 | PVIN | power_in | Power supply input for the switching regulator output stage, with input ceramic capacitors connected between PGND and these pins. |
| 4 | PVIN | power_in | Power supply input for the switching regulator output stage, with input ceramic capacitors connected between PGND and these pins. |
| 5 | N.C. | unconnected | Not connected to the chip; leave open, and confirm no problem if adjacent pins may be shorted in the application. |
| 6 | PGND | power_in | Ground pin for the switching regulator output stage. |
| 7 | PGND | power_in | Ground pin for the switching regulator output stage. |
| 8 | SW | output | Switching node connected to the source of the internal high-side FET and the drain of the internal low-side FET, used for the power inductor and bootstrap capacitor. |
| 9 | SW | output | Switching node connected to the source of the internal high-side FET and the drain of the internal low-side FET, used for the power inductor and bootstrap capacitor. |
| 10 | BST | passive | Connect a 0.1 µF (Typ) bootstrap capacitor between this pin and the SW pins, which supplies the high-side FET gate drive. |
| 11 | OCP_SEL | input | Overcurrent threshold select: high (connected to VREG) sets 1.250 A (Typ) and low (connected to GND) sets 0.625 A (Typ) as the average inductor current limit. |
| 12 | MODE | input | Mode select: high for forced PWM, low or open for AUTO (PWM/LLM), or a applied clock for SYNC mode. |
| 13 | SSCG | input | Spread spectrum select: high (connected to VREG) enables spread spectrum and low (connected to GND) disables it. |
| 14 | RESET | output | Open-drain output reset pin that requires a pull-up resistor to VREG or a supply within the RESET pin absolute maximum rating, with 5 kΩ to 100 kΩ recommended. |
| 15 | GND | power_in | Ground pin for the device. |
| 16 | VOUT_DIS | input | Discharges the VOUT node when connected to VOUT, and must be connected to GND when the discharge function is not required. |
| 17 | VOUT_SNS | input | Inverting input of GmAmp1 used for OVP, SCP and RESET detection and for clamp and phase compensation; connect to the output voltage. |
| 18 | N.C. | unconnected | Not connected to the chip for the BD9P155EFV-C; leave open, and confirm no problem if adjacent pins may be shorted in the application. |
| 19 | VCC_EX | power_in | Power supply input for the internal circuit that supplies VREG when voltage between 3.2 V (VTEXH, Max) and 5.65 V (VEXOVPL, Min) is applied, and must be connected to GND if unused. |
| 20 | VREG | power_out | Outputs 3.3 V (Typ) for the internal circuit, requires a 1.0 µF (Typ) ceramic capacitor, and must not drive external loads other than the OCP_SEL, MODE and SSCG pins and the RESET pull-up. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | HTSSOP-20-EP |
| Category | Power Management ICs |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VVIN, VPVIN | 3.5 | 40 | V | 10 | ||
| Operating Temperature | Ta | -40 | 125 | ˚C | 10 | ||
| SW Minimum ON Time | tONMIN | 50 | ns | 10 | |||
| SW Minimum OFF Time (VREG = 5.0 V) | tOFFMIN | 100 | ns | VREG = 5.0 V | 10 | ||
| Output Current | IOUT | 1 | A | 10 | |||
| Input Capacitor (VIN Continuous Condition) | CIN | 2.3 | µF | VIN Continuous Condition | 10 | ||
| VREG Capacitor | CREG | 0.6 | 1 | 2 | µF | 10 | |
| BST Capacitor | CBST | 0.05 | 0.1 | 0.2 | µF | 10 | |
| Output Voltage Accuracy | -1.75 | 1.75 | % | -40 °C to +125 °C | 1 | ||
| Input Voltage (absolute maximum) | VVIN, VPVIN | -0.3 | 42 | V | 9 | ||
| EN Voltage (absolute maximum) | VEN | -0.3 | 42 | V | 9 | ||
| BST Voltage (absolute maximum) | VBST | -0.3 | 49 | V | 9 | ||
| FB, RESET, MODE, SSCG, OCP_SEL Voltage (absolute maximum) | VFB, VRESET, VMODE, VSSCG, VOCP_SEL | -0.3 | 7 | V | 9 | ||
| VOUT_DIS Voltage (absolute maximum) | VVOUT_DIS | -0.3 | 10 | V | 9 | ||
| VOUT_SNS Voltage (absolute maximum) | VVOUT_SNS | -0.3 | 10 | V | 9 | ||
| VCC_EX Voltage (absolute maximum) | VVCC_EX | -0.3 | 7 | V | 9 | ||
| VREG Voltage (absolute maximum) | VREG | -0.3 | 7 | V | 9 | ||
| Maximum Junction Temperature | Tjmax | 150 | ˚C | 9 | |||
| Shutdown Current | ISDWN | 2.1 | 10 | µA | VEN = 0 V, Ta = -40 ˚C to +105 ˚C | 10 | |
| Quiescent Current from VIN | IQ_VIN1 | 2.1 | 6 | µA | VMODE = 0 V, VVCC_EX = 5 V, VFB = VFB1 x 1.04 (SLEEP) | 10 | |
| Quiescent Current from VIN | IQ_VIN3 | 33 | 66 | µA | VMODE = 5 V, VVCC_EX = 5 V, VFB =VFB1 x 1.04 (No SLEEP) | 10 | |
| Quiescent Current from VCC_EX | IQ_VCC_EX1 | 16 | 60 | µA | VMODE = 0 V, VFB = VFB1 x 1.04 (SLEEP) | 10 | |
| VIN Power On Reset Rising | VPOR_R | 3.6 | 3.8 | 4 | V | VIN Sweep Up | 10 |
| VREG Under Voltage Lockout Falling | VUVLO_F | 2.7 | 2.85 | 3 | V | VREG Sweep Down | 10 |
| VREG Under Voltage Lockout Rising | VUVLO_R | 2.75 | 2.95 | 3.15 | V | VREG Sweep Up | 10 |
| EN Input Voltage High | VENH | 2 | 40 | V | 10 | ||
| EN Input Voltage Low | VENL | 0 | 0.8 | V | 10 | ||
| MODE Input Voltage High | VMODEH | 2 | 5.5 | V | 10 | ||
| OCP_SEL Input Voltage High | VSELH | 2 | 5.5 | V | 10 | ||
| OCP_SEL Input Voltage Low | VSELL | 0.8 | V | 10 | |||
| SSCG Input Voltage High | VSSCGH | 2 | 5.5 | V | 10 | ||
| VREG Voltage | VREG | 3 | 3.3 | 3.6 | V | 11 | |
| VCC_EX OVP Threshold Voltage High | VEXOVPH | 5.85 | 6.2 | 6.55 | V | 11 | |
| VCC_EX OVP Threshold Voltage Low | VEXOVPL | 5.65 | 6 | 6.35 | V | 11 | |
| VOUT_DIS Discharge ON Resistance | RDIS | 75 | 150 | Ω | VEN = 0 V, VOUT_DIS = 0.3 V | 11 | |
| VOUT Discharge Deactivate Voltage | VDISL | 100 | 200 | 300 | mV | VOUT_DIS Sweep Down | 11 |
| Switching Frequency | fSW | 2 | 2.2 | 2.4 | MHz | 11 | |
| Synchronization Frequency Range | fSW_EX | 1.8 | 2.4 | MHz | External Clock Input | 11 | |
| Switching Frequency (Spread Spectrum) | fSWSSR | 1.9 | 2.52 | MHz | VSSCG = 5 V | 11 | |
| Output Voltage (BD9P155EFV-C) VOUT_SNS Voltage, PWM Mode | VOUT_SNS1 | 4.925 | 5.013 | 5.1 | V | VOUT_SNS Voltage, PWM Mode | 11 |
| Enter SLEEP State Voltage (BD9P155EFV-C) | VOUT_SNS2 | 4.963 | 5.076 | 5.188 | V | VOUT_SNS Rising, Light Load Mode | 11 |
| Exit SLEEP State Voltage (BD9P155EFV-C) | VOUT_SNS3 | 4.949 | 5.063 | 5.176 | V | VOUT_SNS Falling, Light Load Mode | 11 |
| Start Delay Time | tDLY | 400 | 800 | µs | 11 | ||
| Soft Start Time | tSS | 2.5 | 3 | 3.9 | ms | VFB1 x 0.1 to VFB1 x 0.9 | 11 |
| High Side FET ON Resistance | RONH | 210 | 440 | mΩ | VBST-VSW = 3.3 V | 11 | |
| Low Side FET ON Resistance | RONL | 140 | 290 | mΩ | VVCC_EX = 3.3 V | 11 | |
| Over Current Protection Threshold | IOCP10 | 1 | 1.25 | 1.5 | A | VOCP_SEL = 5 V | 11 |
| Over Current Protection Threshold | IOCP05 | 0.5 | 0.625 | 0.75 | A | VOCP_SEL = 0 V | 11 |
| Reset Threshold Voltage Low (BD9P155EFV-C) | VRTL | 4.55 | 4.65 | 4.75 | V | 12 | |
| Reset Threshold Voltage High (BD9P155EFV-C) | VRTH | 4.66 | 4.78 | 4.9 | V | 12 | |
| Reset ON Resistance | RRST | 190 | 400 | Ω | VIN = 2 V, VEN = 0 V, IRESET = 1 mA | 12 | |
| Reset Active Time | tRSTNACT | 2 | 3.6 | 5 | ms | 12 | |
| VOUT_SNS OVP Threshold Voltage High (BD9P155EFV-C) | VSNSOVPH | 5.156 | 5.379 | 5.595 | V | 12 | |
| VOUT_SNS OVP Threshold Voltage Low (BD9P155EFV-C) | VSNSOVPL | 5.033 | 5.249 | 5.467 | V | 12 | |
| SCP Threshold Voltage High (BD9P155EFV-C) | VSCPH | 4.25 | 4.5 | 4.75 | V | 12 | |
| SCP Threshold Voltage Low (BD9P155EFV-C) | VSCPL | 3.75 | 4 | 4.25 | V | 12 | |
| Output Voltage for BD9P155EFV-C | VOUT | 5 | V | 10 | |||
| Junction to Ambient (1s board) | θJA | 143 | °C/W | 1s board (Note 4) | 9 | ||
| Junction to Ambient (2s2p board) | θJA | 26.8 | °C/W | 2s2p board (Note 5) | 9 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | Human Body Model (HBM)(Note 1) VESD_HBM ±2 kV Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit | 9 | |
| contacts | copper | 7. To minimize the emission noise from switching node, the distance between the SW pins to inductor should be as short as possible and not to expand the copper area more than necessary. | 49 |
CAD (KiCad official)
- Symbol:
BD9P155EFV-CE2 - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP (KiCad packages3D, STEP)
- 3D model files:
bd9p155efv-ce2-etched.step/bd9p155efv-ce2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bd9p155efv-ce2.step/bd9p155efv-ce2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ROHM Semicon datasheet (60 pp, sha256
f5977b9e0766c210, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).