component
BD9E100FJ-LBGE2
Public Made by Adomby adom
ROHM Semicon DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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BD9E100FJ-LBGE2
ROHM Semicon · DC-DC Converters · SOIC-8
BD9E100FJ-LBGE2 from ROHM Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Connect a 0.1µF bootstrap capacitor between this terminal and SW; the capacitor voltage is the gate drive voltage of the high-side MOSFET. |
| 2 | VIN | power_in | Power supply terminal for the switching regulator and control circuit, with a 7.0V to 36V input range; a 10µF ceramic capacitor is recommended. |
| 3 | EN | input | Enable input: a signal of 0.8V or lower forces shutdown mode and 2.5V or higher enables the device; this terminal must be terminated. |
| 4 | AGND | power_in | Ground terminal for the control circuit. |
| 5 | FB | input | Inverting input node for the gm error amplifier; the output voltage setting resistance is calculated as described on page 22. |
| 6 | COMP | passive | Input terminal for the gm error amplifier output and the output switch current comparator; a frequency phase compensation component is connected here (see page 23 for calculation). |
| 7 | PGND | power_in | Ground terminal for the output stage of the switching regulator. |
| 8 | SW | output | Switch node connected to the high-side MOSFET source and low-side MOSFET drain; the 0.1µF bootstrap capacitor to BOOT and an inductor rated for DC superimposition connect here. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ROHM Semicon |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Current in Operating | IOPR | 1.5 | 2.5 | mA | VFB = 1.1V; No switching | 5 | |
| Supply Current in Standby | ISTBY | 0 | 10 | µA | VEN = 0V | 5 | |
| Reference Voltage | VFB | 0.98 | 1 | 1.02 | V | 5 | |
| FB Input Current | IFB | -1 | 0 | 1 | µA | VFB = 0V | 5 |
| Switching frequency | FOSC | 0.85 | 1 | 1.15 | MHz | 5 | |
| Maximum Duty ratio | Maxduty | 85 | 90 | 95 | % | 5 | |
| UVLO detection voltage | VUVLO | 6.1 | 6.4 | 6.7 | V | VIN falling | 5 |
| UVLO hysteresis voltage | VUVLOHYS | 100 | 200 | 300 | mV | 5 | |
| EN high-level input voltage | VENH | 2.5 | V | 5 | |||
| EN low-level input voltage | VENL | 0.8 | V | 5 | |||
| EN Input current | IEN | 2.1 | 4.2 | 8.4 | µA | VEN = 3V | 5 |
| Soft Start time | TSS | 1.5 | 3 | 6 | msec | EN rising to FB=0.85V | 5 |
| Supply Voltage | VIN | 7 | 36 | V | 5 | ||
| Output Current | IOUT | 0 | 1 | A | 5 | ||
| Output Voltage Range | VRANGE | 1 | V | Note 2: I/O voltage setting with output pulse width not 150nsec (Typ) or less | 5 | ||
| Supply Voltage | VIN | -0.3 | 40 | V | 5 | ||
| EN Input Voltage | VEN | -0.3 | 40 | V | 5 | ||
| Voltage from GND to BOOT | VBOOT | -0.3 | 45 | V | 5 | ||
| Voltage from SW to BOOT | ΔVBOOT | -0.3 | 7 | V | 5 | ||
| FB Input Voltage | VFB | -0.3 | 7 | V | 5 | ||
| COMP Input Voltage | VCOMP | -0.3 | 7 | V | 5 | ||
| SW Input Voltage | VSW | -0.5 | V | Max printed as VIN + 0.3 | 5 | ||
| Allowable Power Dissipation | Pd | 0.67 | W | Mounted on 1-layer 70.0mm x 70.0mm x 1.6mm board; derate 5.36 mW/°C for Ta≥25°C | 5 | ||
| Operating Junction Temperature Range | Tj | -40 | 150 | C | 5 | ||
| Storage Temperature Range | Tstg | -55 | 150 | C | 5 | ||
| Thermal resistance junction-to-ambient | θJA | 185.2 | °C/W | 1 layer board, back side copper foil 70mm x 70mm | 25 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | Provide the input capacitor as close to the VIN terminal as possible on the same plane as the IC. If there is any unused area on the PCB, provide a copper foil plane for the ground node to assist | 24 |
CAD (KiCad official)
- Symbol:
BD9E100FJ-LBGE2 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
bd9e100fj-lbge2-etched.step/bd9e100fj-lbge2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);bd9e100fj-lbge2.step/bd9e100fj-lbge2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ROHM Semicon datasheet (33 pp, sha256
be41189139924dbc, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).