component

AVR128DB48-I/PT

Public Made by Adom

by adom

Microchip Tech Pre-ordered MCUs, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersavr128db48-ifactory-2.0.0extractor-text

Verified AVR128DB48-I/PT

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier mfr, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AVR128DB48-I/PT · TQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 730-page datasheet
  • ✓distributor: lcsc C1019766, digikey 150-AVR128DB48-I/PT-ND, mouser 579-AVR128DB48-I/PT
  • ✓family: TQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-k8zg3kwy/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.712)
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 59 kB, viewers/symbol.html 32 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ avr128db48-i-pt.kicad_sym✓ avr128db48-i-pt.kicad_mod✓ avr128db48-i-pt.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers avr128db48-i-pt: viewers rendered from the public page · Ray
avr128db48-i-pt-etched.glb avr128db48-i-pt: factory component page (tier=mfr) · Ray
avr128db48-i-pt-etched.step avr128db48-i-pt: factory component page (tier=mfr) · Ray
avr128db48-i-pt-hero.glb avr128db48-i-pt: hero GLB from the etched model (keeps the MPN mark) · Ray
avr128db48-i-pt-hero.overlay.json avr128db48-i-pt: hero GLB from the etched model (keeps the MPN mark) · Ray
avr128db48-i-pt.glb Publish 0.1.0 · Ray
avr128db48-i-pt.kicad_mod Publish 0.1.0 · Ray
avr128db48-i-pt.kicad_sym Publish 0.1.0 · Ray
avr128db48-i-pt.lbr Publish 0.1.0 · Ray
avr128db48-i-pt.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 48 pins · Ray

AVR128DB48-I

Microchip Tech · Pre-ordered MCUs · TQFP-48(7x7)

AVR128DB48-I from Microchip Tech, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA5 bidirectional PORTA general-purpose I/O pin 5, with alternate positions for USART0 RxD, SPI0 MISO and TCA0 WO5, and TCD0 WOB.
2 PA6 bidirectional PORTA general-purpose I/O pin 6, with alternate positions for USART0 XCK, SPI0 SCK, TCD0 WOC and CCL OUT.
3 PA7 bidirectional PORTA general-purpose I/O pin 7, which carries CLKOUT and the default ZCD0/1/2 OUT position, with SPI0 SS and TCD0 WOD as further functions.
4 PB0 bidirectional PORTB general-purpose I/O pin 0, powered from the VDDIO2 domain, with alternate positions for USART3 TxD, TCA0 WO0 and CCL LUT4 IN0.
5 PB1 bidirectional PORTB general-purpose I/O pin 1, powered from the VDDIO2 domain, with alternate positions for USART3 RxD, TCA0 WO1 and CCL LUT4 IN1.
6 PB2 bidirectional PORTB general-purpose I/O pin 2, powered from the VDDIO2 domain, with alternate positions for USART3 XCK, TWI0 SDA, TCA0 WO2 and EVSYS EVOUTB.
7 PB3 bidirectional PORTB general-purpose I/O pin 3, powered from the VDDIO2 domain, with alternate positions for USART3 XDIR, TWI0 SCL, TCA0 WO3 and CCL LUT4 OUT.
8 PB4 bidirectional PORTB general-purpose I/O pin 4, powered from the VDDIO2 domain, with alternate positions for USART3 TxD, SPI0 MOSI and TCA0 WO4.
9 PB5 bidirectional PORTB general-purpose I/O pin 5, powered from the VDDIO2 domain, with alternate positions for USART3 RxD, SPI0 MISO and TCA0 WO5.
10 PC0 bidirectional PORTC multi-voltage I/O pin 0 (MVIO, powered from VDDIO2), with alternate positions for USART1 TxD, SPI0 MOSI, TCA0 WO0 and CCL LUT1 IN0.
11 PC1 bidirectional PORTC multi-voltage I/O pin 1 (MVIO, powered from VDDIO2), with alternate positions for USART1 RxD, SPI0 MISO, TCA0 WO1 and CCL LUT1 IN1.
12 PC2 bidirectional PORTC multi-voltage I/O pin 2 (MVIO, powered from VDDIO2), supporting TWI Fm+ with USART1 XCK, SPI0 SCK, TCA0 WO2 and EVSYS EVOUTC.
13 PC3 bidirectional PORTC multi-voltage I/O pin 3 (MVIO, powered from VDDIO2), supporting TWI Fm+ with USART1 XDIR, SPI0 SS, TCA0 WO3 and CCL LUT1 OUT.
14 VDDIO2 power_in Supply for the MVIO-capable I/O pins; in dual-supply mode it may differ from VDD, and in single-supply mode it must be connected to VDD.
15 GND power_in Ground pin common to the VDD, AVDD and VDDIO2 supplies.
16 PC4 bidirectional PORTC multi-voltage I/O pin 4 (MVIO, powered from VDDIO2), with alternate positions for USART1 TxD, SPI0 MOSI and TCA0 WO4.
17 PC5 bidirectional PORTC multi-voltage I/O pin 5 (MVIO, powered from VDDIO2), with alternate positions for USART1 RxD, SPI0 MISO and TCA0 WO5.
18 PC6 bidirectional PORTC multi-voltage I/O pin 6 (MVIO, powered from VDDIO2), with alternate positions for USART1 XCK, SPI0 SCK, TWI0 SDA (client) and TCA0 WO2.
19 PC7 bidirectional PORTC multi-voltage I/O pin 7 (MVIO, powered from VDDIO2), with alternate positions for USART1 XDIR, SPI0 SS, TWI0 SCL (client) and EVSYS EVOUTC.
20 PD0 bidirectional PORTD I/O pin 0 that serves ADC0 input AIN0 and the negative input AINN1 of the analog comparators, with TCD0 WOA and CCL LUT2 IN0 as further functions.
21 PD1 bidirectional PORTD I/O pin 1 that serves ADC0 input AIN1, op amp 0 positive input (OP0 INP) and ZCD0 input (ZCIN), with CCL LUT2 IN1 as a further function.
22 PD2 bidirectional PORTD I/O pin 2 that serves ADC0 input AIN2, analog comparator positive input AINP0, op amp 0 output (OP0 OUT), with EVSYS EVOUTD and CCL LUT2 IN2 as further functions.
23 PD3 bidirectional PORTD I/O pin 3 that serves ADC0 input AIN3, analog comparator negative input AINN0 and op amp 0 negative input (OP0 INN), with CCL LUT2 OUT as a further function.
24 PD4 bidirectional PORTD I/O pin 4 that serves ADC0 input AIN4, analog comparator positive input AINP2 and op amp 1 positive input (OP1 INP).
25 PD5 bidirectional PORTD I/O pin 5 that serves ADC0 input AIN5, analog comparator negative input AINN0 and op amp 1 output (OP1 OUT).
26 PD6 bidirectional PORTD I/O pin 6 that serves ADC0 input AIN6, analog comparator positive input AINP3 and the analog comparator output path, with EVSYS and CCL alternates per the multiplexing table.
27 PD7 bidirectional PORTD I/O pin 7 that also serves as the external voltage reference input VREFA, with ADC0 input AIN7, op amp 1 negative input (OP1 INN) and EVSYS EVOUTD (alternate) as further functions.
28 AVDD power_in Analog supply pin that powers the I/O lines, the external 32.768 kHz oscillator XOSC32K and the analog peripherals; it must be at the same voltage as VDD because AVDD is internally connected to VDD.
29 AGND power_in Analog ground pin listed as AGND in the multiplexing table; the datasheet states that all ground pins are common to VDD, AVDD and VDDIO2.
30 PE0 bidirectional PORTE I/O pin 0 that serves ADC0 input AIN8 and analog comparator positive input AINP1, with USART4 TxD, SPI0 MOSI (alternate) and TCA0 WO0 (alternate) as further functions.
31 PE1 bidirectional PORTE I/O pin 1 that serves ADC0 input AIN9 and op amp 2 positive input (OP2 INP), with USART4 RxD, SPI0 MISO (alternate) and TCA0 WO1 (alternate) as further functions.
32 PE2 bidirectional PORTE I/O pin 2 that serves ADC0 input AIN10, analog comparator positive input AINP2 and op amp 2 output (OP2 OUT), with USART4 XCK, SPI0 SCK (alternate) and EVSYS EVOUTE as further functions.
33 PE3 bidirectional PORTE I/O pin 3 that serves ADC0 input AIN11, op amp 2 negative input (OP2 INN) and ZCD1 input (ZCIN), with USART4 XDIR and SPI0 SS (alternate) as further functions.
34 PF0 bidirectional PORTF I/O pin 0 that is the 32.768 kHz crystal pin XTAL32K1 and ADC0 input AIN16, which cannot be used as a negative differential ADC input; USART2 TxD is an alternate function.
35 PF1 bidirectional PORTF I/O pin 1 that is the 32.768 kHz crystal pin XTAL32K2 and ADC0 input AIN17, which cannot be used as a negative differential ADC input; USART2 RxD is an alternate function.
36 PF2 bidirectional PORTF I/O pin 2, powered from the VDDIO2 domain, that supports TWI Fm+ and ADC0 input AIN18 (not usable as negative differential input), with USART2 XCK, TCD0 WOC and EVSYS EVOUTF as further functions.
37 PF3 bidirectional PORTF I/O pin 3, powered from the VDDIO2 domain, that supports TWI Fm+ and ADC0 input AIN19 (not usable as negative differential input), with USART2 XDIR, TCD0 WOD and CCL LUT3 OUT as further functions.
38 PF4 bidirectional PORTF I/O pin 4, powered from the VDDIO2 domain, that serves ADC0 input AIN20 (not usable as negative differential input), with USART2 TxD (alternate) and TCA0 WO4 (alternate) as further functions.
39 PF5 bidirectional PORTF I/O pin 5, powered from the VDDIO2 domain, that serves ADC0 input AIN21 (not usable as negative differential input), with USART2 RxD (alternate) and TCA0 WO5 (alternate) as further functions.
40 PF6 input Input-only pin PF6 that is the RESET pin; when enabled by the RSTPINCFG fuse it is an external reset input with pull-up enabled on PF6.
41 UPDI bidirectional Dedicated Unified Program and Debug Interface pin used for one-wire UART programming and debugging, with no other function.
42 VDD power_in Supply pin that powers the I/O lines, XOSCHF and the internal voltage regulator; the same voltage must be applied to all VDD and AVDD pins.
43 GND power_in Ground pin common to the VDD, AVDD and VDDIO2 supplies.
44 PA0 bidirectional PORTA I/O pin 0 that is the XTALHF1 external high-frequency crystal pin, with EXTCLK input, USART0 TxD, TCA0 WO0 and CCL LUT0 IN0 as further functions.
45 PA1 bidirectional PORTA I/O pin 1 that is the XTALHF2 external high-frequency crystal pin, with USART0 RxD, TCA0 WO1 and CCL LUT0 IN1 as further functions.
46 PA2 bidirectional PORTA I/O pin 2 that supports TWI Fm+ (SDA), with USART0 XCK, TCA0 WO2, EVSYS EVOUTA and CCL LUT0 IN2 as further functions.
47 PA3 bidirectional PORTA I/O pin 3 that supports TWI Fm+ (SCL), with USART0 XDIR, TCA0 WO3 and CCL LUT1 OUT as further functions.
48 PA4 bidirectional PORTA I/O pin 4 with alternate positions for USART0 TxD, SPI0 MOSI, TCA0 WO4 and TCD0 WOA.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage 1.8 5.5 V Ordering table (Table 41-1) row AVR128DB48-I/PT, TQFP 48, printed as 1.8-5.5V 683
Operating temperature range (Industrial, -I) -40 85 °C Ordering table (Table 41-1) row AVR128DB48-I/PT, printed as -40°C to +85°C 683

CAD (KiCad official)

  • Symbol: AVR128DB48-I
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: avr128db48-i-pt-etched.step / avr128db48-i-pt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); avr128db48-i-pt.step / avr128db48-i-pt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (730 pp, sha256 0d66ae71ca5ec7cc, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF