# AUIRF2804STRL

**Infineon Technologies** · MOSFETs · D2PAK

AUIRF2804STRL from Infineon Technologies, in a D2PAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate terminal of the HEXFET power MOSFET, with a gate-to-source voltage rating of ±20 V and a threshold voltage of 2.0 V to 4.0 V. |
| 2 | D | passive | Drain terminal (also connected to the tab), rated for 40 V drain-to-source breakdown and 195 A package-limited continuous current. |
| 3 | S | passive | Source terminal of the MOSFET, with 270 A silicon-limited continuous drain current and a body diode rated to 270 A continuous source current. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | D2PAK |
| Category | Transistors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-to-Source Breakdown Voltage | V(BR)DSS | 40 |  |  | V | VGS = 0V, ID = 250µA | 2 |
| Static Drain-to-Source On-Resistance (SMD) | RDS(on) |  | 1.5 | 2 | mΩ | VGS = 10V, ID = 75A | 2 |
| Gate Threshold Voltage | VGS(th) | 2 |  | 4 | V | VDS = VGS, ID = 250µA | 2 |
| Forward Transconductance | gfs | 130 |  |  | S | VDS = 10V, ID = 75A | 2 |
| Drain-to-Source Leakage Current | IDSS |  |  | 20 | µA | VDS =40 V, VGS = 0V | 2 |
| Drain-to-Source Leakage Current (125°C) | IDSS |  |  | 250 | µA | VDS =40V,VGS = 0V,TJ =125°C | 2 |
| Gate-to-Source Forward Leakage | IGSS |  |  | 200 | nA | VGS = 20V | 2 |
| Gate-to-Source Reverse Leakage | IGSS | -200 |  |  | nA | VGS = -20V | 2 |
| Total Gate Charge | Qg |  | 160 | 240 | nC | ID = 75A, VDS = 32V, VGS = 10V | 2 |
| Gate-to-Source Charge | Qgs |  | 41 | 62 | nC | ID = 75A, VDS = 32V, VGS = 10V | 2 |
| Gate-to-Drain Charge | Qgd |  | 66 | 99 | nC | ID = 75A, VDS = 32V, VGS = 10V | 2 |
| Continuous Source Current (Body Diode) | IS |  |  | 270 | A | MOSFET symbol showing integral reverse p-n junction diode | 2 |
| Pulsed Source Current (Body Diode) | ISM |  |  | 1080 | A | MOSFET symbol showing integral reverse p-n junction diode | 2 |
| Diode Forward Voltage | VSD |  |  | 1.3 | V | TJ = 25°C,IS = 75A,VGS = 0V | 2 |
| Reverse Recovery Time | trr |  | 56 | 84 | ns | TJ = 25°C ,IF = 75A, VDD = 20V, di/dt = 100A/µs | 2 |
| Reverse Recovery Charge | Qrr |  | 67 | 100 | nC | TJ = 25°C ,IF = 75A, VDD = 20V, di/dt = 100A/µs | 2 |
| Continuous Drain Current (Silicon Limited) | ID |  |  | 270 | A | TC = 25°C, VGS @ 10V | 1 |
| Continuous Drain Current (Silicon Limited) | ID |  |  | 190 | A | TC = 100°C, VGS @ 10V | 1 |
| Continuous Drain Current (Package Limited) | ID |  |  | 195 | A | TC = 25°C, VGS @ 10V | 1 |
| Pulsed Drain Current | IDM |  |  | 1080 | A |  | 1 |
| Maximum Power Dissipation | PD |  |  | 300 | W | TC = 25°C | 1 |
| Linear Derating Factor |  |  |  | 2 | W/°C |  | 1 |
| Gate-to-Source Voltage | VGS | -20 |  | 20 | V |  | 1 |
| Single Pulse Avalanche Energy (Thermally Limited) | EAS |  |  | 540 | mJ |  | 1 |
| Single Pulse Avalanche Energy Tested Value | EAS (tested) |  |  | 1160 | mJ |  | 1 |
| Operating Junction and Storage Temperature Range | TJ, TSTG | -55 |  | 175 | °C |  | 1 |
| Soldering Temperature |  |  |  | 300 | °C | for 10 seconds (1.6mm from case) | 1 |
| Junction-to-Case Thermal Resistance | RθJC |  |  | 0.5 | °C/W |  | 1 |
| Junction-to-Ambient Thermal Resistance | RθJA |  |  | 62 | °C/W |  | 1 |
| Junction-to-Ambient Thermal Resistance (PCB Mount, steady state) | RθJA |  |  | 40 | °C/W | PCB Mount, steady state | 1 |
| Breakdown Voltage Temp. Coefficient | ΔV(BR)DSS/ΔTJ |  | 0.031 |  | V/°C | Reference to 25°C, ID = 1mA | 2 |
| Turn-On Delay Time | td(on) |  | 13 |  | ns | VDD = 20V, ID = 75A, RG= 2.5Ω, VGS = 10V | 2 |
| Rise Time | tr |  | 120 |  | ns | VDD = 20V, ID = 75A, RG= 2.5Ω, VGS = 10V | 2 |
| Turn-Off Delay Time | td(off) |  | 130 |  | ns | VDD = 20V, ID = 75A, RG= 2.5Ω, VGS = 10V | 2 |
| Fall Time | tf |  | 130 |  | ns | VDD = 20V, ID = 75A, RG= 2.5Ω, VGS = 10V | 2 |
| Input Capacitance | Ciss |  | 6450 |  | pF | VGS = 0V, VDS = 25V, ƒ = 1.0MHz | 2 |
| Output Capacitance | Coss |  | 1690 |  | pF | VGS = 0V, VDS = 25V, ƒ = 1.0MHz | 2 |
| Reverse Transfer Capacitance | Crss |  | 840 |  | pF | VGS = 0V, VDS = 25V, ƒ = 1.0MHz | 2 |
| Effective Output Capacitance | Coss eff. |  | 2210 |  | pF | VGS = 0V, VDS = 0V to 32V | 2 |
| Internal Drain Inductance | LD |  | 4.5 |  | nH | Between lead, 6mm (0.25in.) from package and center of die contact | 2 |
| Internal Source Inductance | LS |  | 7.5 |  | nH | Between lead, 6mm (0.25in.) from package and center of die contact | 2 |
| Case-to-Sink Thermal Resistance | RθCS |  | 0.5 |  | °C/W | Flat, Greased Surface | 1 |

## CAD (KiCad official)

- Symbol: `AUIRF2804STRL`
- Footprint: `Package_TO_SOT_SMD:TO-263-2`
- 3D model: D2PAK (KiCad packages3D, STEP)
- 3D model files: `auirf2804strl-etched.step` / `auirf2804strl-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `auirf2804strl.step` / `auirf2804strl.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](docs/auirf2804strl-datasheet.pdf) (13 pp, sha256 `f6a640e1129364f6`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/auirf2804strl-datasheet.pdf)