component
ATTINY814-SSF
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 9d ago |
| viewers | 9d ago |
| attiny814-ssf-etched.glb | 9d ago |
| attiny814-ssf-etched.step | 9d ago |
| attiny814-ssf-hero.glb | 9d ago |
| attiny814-ssf-hero.overlay.json | 9d ago |
| attiny814-ssf.glb | 9d ago |
| attiny814-ssf.kicad_mod | 9d ago |
| attiny814-ssf.kicad_sym | 9d ago |
| attiny814-ssf.lbr | 9d ago |
| attiny814-ssf.step | 9d ago |
| package.json | 9d ago |
| page.json | 9d ago |
| README.md | 9d ago |
ATTINY814-SSF
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · SOIC-14
ATTINY814-SSF from Microchip Tech, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply pin for the device, placed on the VDD power domain. |
| 2 | PA4 | bidirectional | General-purpose I/O pin PA4 on the VDD domain, also ADC0 input AIN4, PTC X0/Y0, USART0 XDIR (alternate position), SPI0 SS, TCA0 WO4 and WOA, and CCL LUT0-OUT. |
| 3 | PA5 | bidirectional | General-purpose I/O pin PA5 on the VDD domain, also ADC0 input AIN5, PTC X1/Y1, DAC0 OUT, TCA0 WO5 and WO, and TCB1 WOB. |
| 4 | PA6 | bidirectional | General-purpose I/O pin PA6 on the VDD domain, also ADC0 input AIN6, PTC X2/Y2, AC0 negative input AINN0, and DAC0 OUT (PA6 is the DAC0 output pin). |
| 5 | PA7 | bidirectional | General-purpose I/O pin PA7 on the VDD domain, also ADC0 input AIN7, PTC X3/Y3, AC0 positive input AINP0, and CCL LUT1-OUT. |
| 6 | PB3 | bidirectional | General-purpose I/O pin PB3, also the TOSC1 crystal oscillator input, USART0 RxD (alternate position) and TCA0 WO0 (alternate position). |
| 7 | PB2 | bidirectional | General-purpose I/O pin PB2, also the TOSC2 crystal oscillator output, EVSYS EVOUT1, USART0 TxD and TCA0 WO2. |
| 8 | PB1 | bidirectional | General-purpose I/O pin PB1, also ADC0 input AIN10, PTC X4/Y4, USART0 XCK, TWI0 SDA and TCA0 WO1. |
| 9 | PB0 | bidirectional | General-purpose I/O pin PB0, also ADC0 input AIN11, PTC X5/Y5, USART0 XDIR, TWI0 SCL and TCA0 WO0. |
| 10 | PA0 (RESET/UPDI) | bidirectional | Pin PA0 is the RESET or single-pin UPDI programming/debug interface, selected by the RSTPINCFG fuse; it can also serve as ADC0 input AIN0 and CCL LUT0-IN0 when used as GPIO. |
| 11 | PA1 | bidirectional | General-purpose I/O pin PA1, also ADC0 input AIN1, USART0 TxD (alternate position), SPI0 MOSI, TWI0 SDA (alternate position) and CCL LUT0-IN1. |
| 12 | PA2 | bidirectional | General-purpose I/O pin PA2, also EVSYS EVOUT0, ADC0 input AIN2, USART0 RxD (alternate position), SPI0 MISO, TWI0 SCL (alternate position) and CCL LUT0-IN2. |
| 13 | PA3 (EXTCLK) | bidirectional | General-purpose I/O pin PA3, also the external clock input EXTCLK, ADC0 input AIN3, USART0 XCK (alternate position), SPI0 SCK and TCA0 WO3. |
| 14 | GND | power_in | Ground reference pin for the device. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-14 |
| Category | Embedded Processors & Controllers |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 2.7 | 5.5 | V | 560 | ||
| Operating temperature range | -40 | 125 | °C | 560 | |||
| Max. CPU speed | 16 | MHz | 560 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | including indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. In the Self Capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor. | 461 |
CAD (KiCad official)
- Symbol:
ATTINY814-SSF - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
attiny814-ssf-etched.step/attiny814-ssf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);attiny814-ssf.step/attiny814-ssf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (596 pp, sha256
c2392fe1c4c9666a, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).