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ATSAML11E15A-AFKPH

Microchip Tech · Pre-ordered MCUs · TQFP-32(7x7)

ATSAML11E15A-AFKPH from Microchip Tech, in a TQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA00/XIN32 bidirectional General-purpose I/O PA00 on the VDDANA domain, alternately the 32.768 kHz crystal oscillator input XIN32 (also EXTINT[0], OA1NEG, SERCOM1/PAD[0], TC2/WO[0]) and resets to I/O in high-impedance state.
2 PA01/XOUT32 bidirectional General-purpose I/O PA01 on the VDDANA domain, alternately the 32.768 kHz crystal oscillator output XOUT32 (also EXTINT[1], XY[1], OA1POS, SERCOM1/PAD[1], TC2/WO[1]) and resets to I/O in high-impedance state.
3 PA02 bidirectional General-purpose I/O PA02 on the VDDANA domain with analog input AIN[0], VOUT DAC output and OA0NEG, and this pin must have a transition time above 50 us to avoid affecting XOSC32 cycle-to-cycle jitter.
4 PA03 bidirectional General-purpose I/O PA03 on the VDDANA domain with analog inputs VREFA and AIN[1], EXTINT[3], XY[3], OA2NEG and SERCOM0/PAD[3].
5 PA04 bidirectional General-purpose I/O PA04 on the VDDANA domain with analog input VREFB and AIN[2], EXTINT[4], OA2OUT, SERCOM0/PAD[0], TC0/WO[0] and CCL input IN[0].
6 PA05 bidirectional General-purpose I/O PA05 on the VDDANA domain with analog input AIN[3], EXTINT[5], XY[4], OA2POS, SERCOM0/PAD[1], TC0/WO[1] and CCL input IN[1].
7 PA06 bidirectional General-purpose I/O PA06 on the VDDANA domain with analog input AIN[4], EXTINT[6], XY[5], OA0POS, SERCOM0/PAD[2], TC1/WO[0] and CCL input IN[2].
8 PA07 bidirectional General-purpose I/O PA07 on the VDDANA domain with analog input AIN[5], EXTINT[7], OA0OUT, SERCOM0/PAD[3], TC1/WO[1] and CCL output OUT[0].
9 VDDANA power_in Analog supply voltage, 1.62V to 3.63V, which must equal VDDIO and needs 100 nF and 10 uF decoupling close to the device; a ferrite bead may isolate it from digital noise.
10 GNDANA power_in Ground for the analog power domain.
11 PA08 bidirectional General-purpose I/O PA08 on the VDDIO domain with NMI, analog input AIN[6], XY[6], SERCOM1/PAD[0], SERCOM2/PAD[0], RTC/IN[0] and CCL input IN[3].
12 PA09 bidirectional General-purpose I/O PA09 on the VDDIO domain with EXTINT[0], analog input AIN[7], XY[7], SERCOM1/PAD[1], SERCOM2/PAD[1], RTC/IN[1] and CCL input IN[4].
13 PA10 bidirectional General-purpose I/O PA10 on the VDDIO domain with EXTINT[1], analog input AIN[8], XY[8], SERCOM1/PAD[2], SERCOM2/PAD[2], GCLK_IO[4] and CCL input IN[5].
14 PA11 bidirectional General-purpose I/O PA11 on the VDDIO domain with EXTINT[2], analog input AIN[9], XY[9], SERCOM1/PAD[3], SERCOM2/PAD[3], GCLK_IO[3] and CCL output OUT[1].
15 PA14 / XOSC bidirectional General-purpose I/O PA14 on the VDDIO domain, alternately the crystal oscillator input XIN (also EXTINT[3], XY[10], SERCOM2/PAD[2], SERCOM0/PAD[2], TC0/WO[0] and GCLK_IO[0]).
16 PA15/XOUT bidirectional General-purpose I/O PA15 on the VDDIO domain, alternately the crystal oscillator output XOUT (also EXTINT[4], XY[11], SERCOM2/PAD[3], SERCOM0/PAD[3], TC0/WO[1] and GCLK_IO[1]).
17 PA16 bidirectional High-sink General-purpose I/O PA16 on the VDDIO domain with EXTINT[5], XY[12], SERCOM1/PAD[0], SERCOM0/PAD[0], RTC/IN[2], GCLK_IO[2] and CCL input IN[0]; high-sink pins have different properties than standard pins.
18 PA17 bidirectional High-sink General-purpose I/O PA17 on the VDDIO domain with EXTINT[6], XY[13], SERCOM1/PAD[1], SERCOM0/PAD[1], RTC/IN[3], GCLK_IO[3] and CCL input IN[1]; high-sink pins have different properties than standard pins.
19 PA18 bidirectional General-purpose I/O PA18 on the VDDIO domain with EXTINT[7], XY[14], SERCOM1/PAD[2], SERCOM0/PAD[2], TC2/WO[0], RTC/OUT[0], AC/CMP[0] and CCL input IN[2].
20 PA19 bidirectional General-purpose I/O PA19 on the VDDIO domain with EXTINT[0], XY[15], SERCOM1/PAD[3], SERCOM0/PAD[3], TC2/WO[1], RTC/OUT[1], AC/CMP[1] and CCL output OUT[0].
21 PA22 bidirectional High-sink General-purpose I/O PA22 on the VDDIO domain with EXTINT[1], XY[16], SERCOM0/PAD[0], SERCOM2/PAD[0], TC0/WO[0], RTC/OUT[2] and GCLK_IO[2]; high-sink pins have different properties than standard pins.
22 PA23 bidirectional High-sink General-purpose I/O PA23 on the VDDIO domain with EXTINT[2], XY[17], SERCOM0/PAD[1], SERCOM2/PAD[1], TC0/WO[1], RTC/OUT[3] and GCLK_IO[1]; high-sink pins have different properties than standard pins.
23 PA24 bidirectional General-purpose I/O PA24 on the VDDIO domain with EXTINT[3], SERCOM0/PAD[2], SERCOM2/PAD[2] and TC1/WO[0].
24 PA25 bidirectional General-purpose I/O PA25 on the VDDIO domain with EXTINT[4], SERCOM0/PAD[3], SERCOM2/PAD[3] and TC1/WO[1].
25 PA27 bidirectional General-purpose I/O PA27 on the VDDIO domain with EXTINT[5] and GCLK_IO[0].
26 RESET input External reset input with an internal pull-up resistor, on the VDDIO domain.
27 VDDCORE passive Core supply of 0.9V to 1.2V typical, which is the linear regulator output needing 100 nF and 1 uF decoupling in linear mode and must be fed from VDDOUT via a 10 uH inductor in switching mode.
28 GND power_in Ground for the digital power domain; the QFN exposed pad must be connected to GND.
29 VDDOUT power_out On-chip switching regulator output that requires a 10 uH inductor to VDDCORE in switching regulator mode and is not connected in linear regulator mode.
30 VDDIO power_in Digital supply voltage, 1.62V to 3.63V, which must equal VDDANA and needs 100 nF and 10 uF decoupling close to the device.
31 PA30 / SWCLK input Serial Wire Debug clock SWCLK on the VDDIO domain, the default function of PA30 that enables debugger probe detection, with an internal pull-up and a pull-up resistor recommended for noise immunity; pin is also XOSC32 jitter-sensitive per Table 4-3 (TQFP32 PA02 and PA31).
32 PA31 / SWDIO bidirectional Serial Wire Debug bidirectional data pin SWDIO on the VDDIO domain, also EXTINT[7], XY[19], SERCOM1/PAD[3], TC1/WO[1] and CCL output OUT[1]; this is a high-sink pin and its transition time must exceed 50 us for XOSC32 jitter minimization.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating voltage range VDDIO 1.62 3.63 V Voltage range, nominal: 1.62V - 3.63V, 3.3V (VDDIO supply) 24
Core voltage range VDDCORE 0.9 1.2 V Voltage range (VDDCORE, core, embedded memories, peripherals) 24
Operating temperature range -40 125 °C Operating Conditions: -40ºC to +125ºC (grade F, Matte Sn Plating) 1
Maximum CPU clock frequency 0 32 MHz Operating Conditions: DC to 32 MHz 1

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. In self-capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor. 976

CAD (KiCad official)

  • Symbol: ATSAML11E15A-AFKPH
  • Footprint: Package_QFP:TQFP-32_7x7mm_P0.8mm
  • 3D model: TQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: atsaml11e15a-afkph-etched.step / atsaml11e15a-afkph-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsaml11e15a-afkph.step / atsaml11e15a-afkph.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1127 pp, sha256 ee9c04451141173b, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF