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ATSAML10D15A-MU

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Microchip Tech Pre-ordered MCUs, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatsaml10d15a-mufactory-2.0.0extractor-text

Changed since verified ATSAML10D15A-MU

by Ray · last 30 Oct 2026 · 1 record · files changed since
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 25 pinschanged since
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATSAML10D15A-MU · QFN-24-EP(4x4) · 25 pins
  • ✓copper: 25 copper pads, none touching another net
  • ✓datasheet: all 25 pin names found in the 1127-page datasheet
  • ✓distributor: lcsc C1338323, digikey ATSAML10D15A-MU-ND, mouser 579-ATSAML10D15A-MU
  • ✓family: QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-blif85ei/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 25 pins = 25 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 25 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! atsaml10d15a-mu.kicad_sym✓ atsaml10d15a-mu.kicad_mod✓ atsaml10d15a-mu.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs atsaml10d15a-mu: hero re-rendered with the chip (after the 10-30 render outage) · Ray 5d ago
viewers atsaml10d15a-mu: symbol repaired (body fitted to the names) · Ray 10h ago
atsaml10d15a-mu-etched.glb Publish 0.1.0 · Ray 5d ago
atsaml10d15a-mu-etched.step atsaml10d15a-mu: factory component page (tier=mfr) · Ray 5d ago
atsaml10d15a-mu-hero.glb atsaml10d15a-mu: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
atsaml10d15a-mu-hero.overlay.json Publish 0.1.0 · Ray 5d ago
atsaml10d15a-mu.glb Publish 0.1.0 · Ray 5d ago
atsaml10d15a-mu.kicad_mod Publish 0.1.0 · Ray 5d ago
atsaml10d15a-mu.kicad_sym atsaml10d15a-mu: symbol repaired (body fitted to the names) · Ray 10h ago
atsaml10d15a-mu.lbr atsaml10d15a-mu: symbol repaired (body fitted to the names) · Ray 10h ago
atsaml10d15a-mu.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
verification.json Verified: Published by the parts factory: tier mfr, 25 pins · Ray 5d ago

ATSAML10D15A-MU

Microchip Tech · Pre-ordered MCUs · QFN-24-EP(4x4)

ATSAML10D15A-MU from Microchip Tech, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA31 / SWDIO bidirectional High Sink GPIO on VDDIO (EXTINT[7], XY[19], SERCOM1/PAD[3], TC1/WO[1], GCLK/OUT[1]) that serves as the SWDIO debug data pin when the SWCLK probe detection selects SWDIO; reset state I/O, Hi-Z.
2 PA00/XIN32 bidirectional GPIO on the VDDANA domain that doubles as XIN32, the 32.768 kHz crystal oscillator input or external clock input (analog input for crystal, digital input for external clock); reset state I/O, Hi-Z.
3 PA01/XOUT32 bidirectional GPIO on the VDDANA domain that doubles as XOUT32, the 32.768 kHz crystal oscillator output (analog output); reset state I/O, Hi-Z.
4 PA02 bidirectional GPIO on the VDDANA domain with AIN[0], VOUT (DAC) and OA0NEG analog functions; its transition time must be greater than 50 us to avoid affecting XOSC32 cycle-to-cycle jitter.
5 PA03 bidirectional GPIO on the VDDANA domain with VREFA, AIN[1], OA2NEG and SERCOM0/PAD[3] functions; reset state I/O, Hi-Z.
6 PA04 bidirectional GPIO on the VDDANA domain with VREFB, AIN[2], OA2OUT, TC0/WO[0] and CCL IN[0] functions; reset state I/O, Hi-Z.
7 PA05 bidirectional GPIO on the VDDANA domain with AIN[3], OA2POS, TC0/WO[1] and CCL IN[1] functions; reset state I/O, Hi-Z.
8 VDDANA power_in Analog power domain supply, 1.62 V to 3.63 V, which must be the same voltage applied to VDDIO; decoupled with 100 nF and 10 µF close to the device.
9 GNDANA power_in Ground for the analog power domain.
10 PA08 bidirectional VDDIO-domain GPIO with NMI, AIN[6], XY[6], SERCOM1/PAD[0], SERCOM2/PAD[0] and RTC/IN[0] functions; reset state I/O, Hi-Z.
11 PA14 / XIN bidirectional VDDIO-domain GPIO that doubles as XIN, the main 0.4 to 32 MHz crystal oscillator input or external clock input; reset state I/O, Hi-Z.
12 PA15/XOUT bidirectional VDDIO-domain GPIO that doubles as XOUT, the output of the main 0.4 to 32 MHz crystal oscillator; reset state I/O, Hi-Z.
13 PA16 bidirectional High Sink VDDIO-domain GPIO (drive limits differ from normal pins) with EXTINT[5], SERCOM1/PAD[0], SERCOM0/PAD[0], RTC/IN[2] and GCLK_IO[2] functions; reset state I/O, Hi-Z.
14 PA17 bidirectional High Sink VDDIO-domain GPIO (drive limits differ from normal pins) with EXTINT[6], SERCOM1/PAD[1], SERCOM0/PAD[1], RTC/IN[3] and GCLK_IO[3] functions; reset state I/O, Hi-Z.
15 PA18 bidirectional VDDIO-domain GPIO with EXTINT[7], SERCOM1/PAD[2], SERCOM0/PAD[2], TC2/WO[0], RTC/OUT[0] and AC/CMP[0] functions; reset state I/O, Hi-Z.
16 PA19 bidirectional VDDIO-domain GPIO with EXTINT[0], SERCOM1/PAD[3], SERCOM0/PAD[3], TC2/WO[1], RTC/OUT[1] and AC/CMP[1] functions; reset state I/O, Hi-Z.
17 PA22 bidirectional High Sink VDDIO-domain GPIO (drive limits differ from normal pins) with EXTINT[1], SERCOM0/PAD[0], SERCOM2/PAD[0], TC0/WO[0], RTC/OUT[2] and GCLK_IO[2] functions; reset state I/O, Hi-Z.
18 PA23 bidirectional High Sink VDDIO-domain GPIO (drive limits differ from normal pins) with EXTINT[2], SERCOM0/PAD[1], SERCOM2/PAD[1], TC0/WO[1], RTC/OUT[3] and GCLK_IO[1] functions; reset state I/O, Hi-Z.
19 RESET input External reset input with an internal pull-up resistor (reset state I, PU), so an external pull-up is optional.
20 VDDCORE power_in Core supply voltage of 0.9 V to 1.2 V typical; it is the core supply output and external decoupling pin in linear regulator mode and the core supply input (connected to VDDOUT via a 10 µH inductor) in switching regulator mode, with 100 nF and 1 µF decoupling.
21 GND power_in Ground.
22 VDDOUT power_out On-chip switching-mode regulator output, connected to VDDCORE through a 10 µH inductor in switching regulator mode and not connected in linear regulator mode.
23 VDDIO power_in Digital supply voltage of 1.62 V to 3.63 V, which must be the same voltage applied to VDDANA; decoupled with 100 nF and 10 µF close to the device.
24 PA30 / SWCLK bidirectional VDDIO-domain GPIO that defaults to the SWCLK debug clock function (reset state SWCLK, I, PU) used for debugger probe detection, and a pull-up on SWCLK is recommended for noise immunity.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-24-EP(4x4)
Category Embedded Processors & Controllers
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating voltage range, nominal (VDDIO) VDDIO 1.62 3.3 3.63 V Voltage range, nominal; same source must be applied to VDDIO and VDDANA 24
Operating voltage range, nominal (VDDANA) VDDANA 1.62 3.3 3.63 V Voltage range, nominal; same source must be applied to VDDIO and VDDANA 24
Core supply voltage range (internal regulator output) VDDCORE 0.9 1.2 V Voltage range; core domain supply, generated internally 24
Operating temperature range (ordering suffix U) -40 85 °C Ordering code suffix U = -40 to +85°C 16

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin indium tin oxide (ITO) sensor grids. The PTC requires one pin per X-line and one pin per Y-line. In self-capacitance mode, the PTC requires only one pin (Y-line) for each touch sensor. 976

CAD (KiCad official)

  • Symbol: ATSAML10D15A-MU
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: atsaml10d15a-mu-etched.step / atsaml10d15a-mu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsaml10d15a-mu.step / atsaml10d15a-mu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1127 pp, sha256 ee9c04451141173b, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF