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ATSAM3U2CA-AU

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Microchip Tech MICROCHIP, LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ATSAM3U2CA-AU

Microchip Tech · MICROCHIP · LQFP-100(14x14)

ATSAM3U2CA-AU from Microchip Tech, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDANA power_in Powers the ADC cells with a voltage range of 2.0-3.6 V.
2 ADVREF passive Voltage reference for the 10-bit ADC; conversions extend from 0 V to ADVREF.
3 GNDANA power_in Separate ground pin for the ADC supply domain (VDDANA).
4 AD12BVREF passive Voltage reference for the 12-bit ADC; conversions extend from 0 V to AD12BVREF.
5 PA22/PGMD14 bidirectional PIOA line 22 multiplexed with the PGMD14 parallel programming data function; listed as an ADC input pin in the errata.
6 PA30 bidirectional PIOA line 30, listed as an ADC input pin in the errata; Table 35-4 maps TIOA2 of TC0 to this pin (peripheral B).
7 PB3 bidirectional PIOB line 3, listed as an ADC input pin in the errata.
8 PB4 bidirectional PIOB line 4, listed as an ADC input pin in the errata; Table 35-4 maps TCLK1 of TC0 to this pin.
9 VDDCORE power_in Powers the core, embedded memories and peripherals with a voltage range of 1.62-1.95 V.
10 PA13/PGMD5 bidirectional PIOA line 13 used as SPI MISO (peripheral A) per Table 31-2, also PGMD5 programming data.
11 PA14/PGMD6 bidirectional PIOA line 14 used as SPI MOSI (peripheral A) per Table 31-2, also PGMD6 programming data.
12 PA15/PGMD7 bidirectional PIOA line 15 used as SPI SPCK (peripheral A) per Table 31-2, also PGMD7 programming data.
13 PA16/PGMD8 bidirectional PIOA line 16 used as SPI NPCS0 (peripheral A) per Table 31-2, also PGMD8 programming data.
14 PA17/PGMD9 bidirectional PIOA line 17 with PGMD9 parallel programming data function.
15 PB16 bidirectional PIOB line 16 general-purpose I/O.
16 PB15 bidirectional PIOB line 15 general-purpose I/O.
17 PA18/PGMD10 bidirectional PIOA line 18 with PGMD10 parallel programming data function.
18 PA19/PGMD11 bidirectional PIOA line 19 used as SPI NPCS3 (peripheral B) per Table 31-2, also PGMD11 programming data.
19 PA20/PGMD12 bidirectional PIOA line 20 with PGMD12 parallel programming data function.
20 PA21/PGMD13 bidirectional PIOA line 21 with PGMD13 parallel programming data function.
21 PA23/PGMD15 bidirectional PIOA line 23 with PGMD15 parallel programming data function.
22 VDDIO power_in Powers the peripheral I/O lines with a voltage range of 1.62-3.6 V.
23 PA24 bidirectional PIOA line 24 used as TWD1 (peripheral A) per Table 32-4.
24 PA25 bidirectional PIOA line 25 used as TWCK1 (peripheral A) per Table 32-4.
25 PA26 bidirectional PIOA line 26 used as SSC TD (peripheral A) per Table 30-2 and TC0 TCLK2 (peripheral B) per Table 35-4.
26 PA0/PGMNCMD bidirectional PIOA line 0 used as TC0 TIOB0 (peripheral A), SPI NPCS1 (peripheral B), and PGMNCMD programming command.
27 PA1/PGMRDY bidirectional PIOA line 1 used as TC0 TIOA0 (peripheral A), SPI NPCS2 (peripheral B), and PGMRDY programming status.
28 PA2/PGMNOE bidirectional PIOA line 2 used as TC0 TCLK0 (peripheral A), ADC12B trigger AD12BTRG (peripheral B), and PGMNOE programming control.
29 PA3/PGMNVALID bidirectional PIOA line 3 used as HSMCI MCCK (peripheral A) per Table 36-2, also PGMNVALID programming control.
30 PA4/PGMM0 bidirectional PIOA line 4 used as HSMCI MCCDA (peripheral A) per Table 36-2, also PGMM0 programming mode.
31 PA5/PGMM1 bidirectional PIOA line 5 used as HSMCI MCDA0 (peripheral A) per Table 36-2, also PGMM1 programming mode.
32 PA6/PGMM2 bidirectional PIOA line 6 used as HSMCI MCDA1 (peripheral A) per Table 36-2, also PGMM2 programming mode.
33 PA7/PGMM3 bidirectional PIOA line 7 used as HSMCI MCDA2 (peripheral A) per Table 36-2, also PGMM3 programming mode.
34 VDDCORE power_in Powers the core, embedded memories and peripherals with a voltage range of 1.62-1.95 V.
35 GND power_in Ground shared by the VDDCORE and VDDIO supply domains.
36 VDDIO power_in Powers the peripheral I/O lines with a voltage range of 1.62-3.6 V.
37 PA8/PGMD0 bidirectional PIOA line 8 used as HSMCI MCDA3 (peripheral A) per Table 36-2, also PGMD0 programming data.
38 PA9/PGMD1 bidirectional PIOA line 9 used as TWD0 (peripheral A) per Table 32-4, also PGMD1 programming data.
39 PA10/PGMD2 bidirectional PIOA line 10 used as TWCK0 (peripheral A) per Table 32-4, also PGMD2 programming data.
40 PA11/PGMD3 bidirectional PIOA line 11 used as UART URXD (peripheral A) per Table 33-2, also PGMD3 programming data.
41 PA12/PGMD4 bidirectional PIOA line 12 used as UART UTXD (peripheral A) per Table 33-2, also PGMD4 programming data.
42 FWUP input Fast wake-up input feeding a falling edge detector; must be high together with NRST, NRSTB and JTAGSEL to enable boundary scan during power-up.
43 ERASE input Flash erase pin; the datasheet references it for reprogramming Flash content (Section 6.7) but the detailed behaviour is not in the extracted text.
44 TST input Test select pin: low at power-up selects normal operation, high selects test or FFPI mode, and it has an internal pull-down of about 15 kΩ.
45 VDDBU power_in Powers the slow clock oscillator and part of the System Controller with a voltage range of 1.62-3.6 V; it must be supplied before or at the same time as VDDIO and VDDCORE.
46 GNDBU power_in Separate ground pin for the VDDBU backup supply domain.
47 NRSTB input Reset input that, together with FWUP, NRST and JTAGSEL high while TST is low, enables IEEE 1149.1 boundary scan during power-up.
48 JTAGSEL input JTAG selection input: when low, SW-DP or JTAG-DP mode is selected, and a chip reset must follow any change of its state.
49 XOUT32 output Output of the 32.768 kHz crystal oscillator; left unconnected if the crystal oscillator is not used.
50 XIN32 input Input of the 32.768 kHz crystal oscillator, which can also be driven by an external clock when OSCBYPASS is set.
51 TDI input JTAG Test Data In input.
52 VDDOUT power_out Output of the embedded 1.8 V voltage regulator.
53 VDDIN power_in Supply input that powers the voltage regulator.
54 TDO/TRACESWO output JTAG Test Data Out, or asynchronous trace output TRACESWO in SWD mode; it is in input mode outside debug and needs an external 100 kΩ pull-up.
55 TMS/SWDIO bidirectional JTAG Test Mode Select, or SWDIO serial wire data input/output in SWD mode.
56 TCK/SWCLK input JTAG Test Clock, or SWCLK serial wire clock in SWD mode.
57 NRST bidirectional Microcontroller reset, active low, configured as input/output.
58 PB24 bidirectional PIOB line 24 general-purpose I/O.
59 VDDCORE power_in Powers the core, embedded memories and peripherals with a voltage range of 1.62-1.95 V.
60 VDDIO power_in Powers the peripheral I/O lines with a voltage range of 1.62-3.6 V.
61 GND power_in Ground shared by the VDDCORE and VDDIO supply domains.
62 PB23 bidirectional PIOB line 23 general-purpose I/O.
63 PB22 bidirectional PIOB line 22 general-purpose I/O.
64 PB21 bidirectional PIOB line 21 general-purpose I/O.
65 PB20 bidirectional PIOB line 20 general-purpose I/O.
66 PB19 bidirectional PIOB line 19 general-purpose I/O.
67 PB18 bidirectional PIOB line 18 general-purpose I/O.
68 PB17 bidirectional PIOB line 17 general-purpose I/O.
69 PB14 bidirectional PIOB line 14 general-purpose I/O.
70 PB10 bidirectional PIOB line 10 general-purpose I/O.
71 PB9 bidirectional PIOB line 9 general-purpose I/O.
72 GNDPLL power_in Separate ground for PLL A, UPLL and the 3-20 MHz oscillator.
73 VDDPLL power_in Powers PLL A, UPLL and the 3-20 MHz oscillator with a voltage range of 1.62-1.95 V.
74 XOUT output Output of the 3-20 MHz crystal oscillator.
75 XIN input Input of the 3-20 MHz crystal oscillator.
76 DHSDP bidirectional High Speed USB Device Port differential data plus line of the embedded transceiver.
77 DHSDM bidirectional High Speed USB Device Port differential data minus line of the embedded transceiver.
78 VBG passive Bandgap voltage pin; the provided text gives no further electrical limits for it.
79 VDDUTMI power_in Powers the UTMI+ interface with a voltage range of 3.0-3.6 V (3.3 V nominal).
80 DFSDM bidirectional Full-speed USB data minus line of the UTMI+ interface (name-based; no further description in the extracted text).
81 DFSDP bidirectional Full-speed USB data plus line of the UTMI+ interface (name-based; no further description in the extracted text).
82 GNDUTMI power_in Separate ground for the VDDUTMI supply domain.
83 VDDCORE power_in Powers the core, embedded memories and peripherals with a voltage range of 1.62-1.95 V.
84 PA28 bidirectional PIOA line 28 used as SSC TK (peripheral A) per Table 30-2.
85 PA29 bidirectional PIOA line 29 used as SSC RK (peripheral A) per Table 30-2.
86 PA31 bidirectional PIOA line 31 used as SSC RF (peripheral A) per Table 30-2 and TC0 TIOB2 (peripheral B) per Table 35-4.
87 VDDCORE power_in Powers the core, embedded memories and peripherals with a voltage range of 1.62-1.95 V.
88 VDDIO power_in Powers the peripheral I/O lines with a voltage range of 1.62-3.6 V.
89 GND power_in Ground shared by the VDDCORE and VDDIO supply domains.
90 PB0 bidirectional PIOB line 0 general-purpose I/O.
91 PB1 bidirectional PIOB line 1 general-purpose I/O.
92 PB2 bidirectional PIOB line 2 general-purpose I/O.
93 PB11 bidirectional PIOB line 11 general-purpose I/O.
94 PB12 bidirectional PIOB line 12 general-purpose I/O.
95 PB13 bidirectional PIOB line 13 general-purpose I/O.
96 PA27 bidirectional PIOA line 27 used as SSC RD (peripheral A) per Table 30-2.
97 PB5 bidirectional PIOB line 5 used as TC0 TIOA1 (peripheral A) per Table 35-4.
98 PB6 bidirectional PIOB line 6 used as TC0 TIOB1 (peripheral A) per Table 35-4.
99 PB7 bidirectional PIOB line 7 general-purpose I/O.
100 PB8 bidirectional PIOB line 8 general-purpose I/O.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Core supply voltage range (VDDCORE pins) VDDCORE 1.62 1.95 V Powers core, embedded memories and peripherals 17
I/O supply voltage range (VDDIO pins) VDDIO 1.62 3.6 V Powers peripheral I/O lines 17
Backup supply voltage range (VDDBU pin) VDDBU 1.62 3.6 V Powers Slow Clock oscillator and part of System Controller; must be supplied before or at the same time as VDDIO and VDDCORE 17
PLL supply voltage range (VDDPLL pin) VDDPLL 1.62 1.95 V Powers PLL A, UPLL and 3-20 MHz oscillator 17
UTMI+ supply voltage range (VDDUTMI pin) VDDUTMI 3 3.3 3.6 V Powers UTMI+ interface; 3.3 V nominal 17
ADC supply voltage range (VDDANA pin) VDDANA 2 3.6 V Powers ADC cells 17
VDDIO minimum operating voltage before VDDCORE reaches VDDCORE(min) VDDIO 1.6 V VDDIO must reach this voltage before VDDCORE reaches VDDCORE(min) 17
VDDIO rising slope when VDDCORE rises at the same time VDDIO 5 V/ms VDDCORE rises at the same time as VDDIO; slope must be higher than or equal to this value 17
Voltage regulator static (quiescent) current 700 uA Voltage regulator in Normal mode 17
Voltage regulator output current 150 mA Voltage regulator in Normal mode 17
Voltage regulator quiescent current at low load 7 uA Wait mode or when output current is low 17
Voltage regulator shutdown current 1 uA Voltage regulator in Shutdown mode; output driven internally to GND 17
Voltage regulator default output voltage VDDOUT 1.8 V Default output voltage of the internal regulator 17
Voltage regulator startup time to Normal mode 400 us Startup time to reach Normal mode 17
Backup mode current consumption 2.5 uA Backup mode; current consumption on VDDBU 24
Backup mode wake-up time 0.5 ms Wake-up from Backup mode 24
Wait mode wake-up time 10 us Wake-up from Wait mode 24
Supply monitor programmable threshold range (VDDUTMI) VDDUTMI 1.9 3.4 V Programmable in 100 mV steps 269
Maximum CPU operating speed 96 MHz Maximum operating speed of the Cortex-M3 core 1
I/O pad maximum frequency (HSMCI and SPI clock lines) 65 MHz High-speed pads on HSMCI and SPI clock lines 25
I/O pad maximum frequency (other lines) 35 MHz High-speed pads on other I/O lines 25
3-20 MHz crystal oscillator frequency 3 20 MHz Main clock crystal oscillator 446
3-20 MHz crystal oscillator maximum startup time 62 ms Maximum startup time with MOSCXTCNT at its maximum value 446
Slow clock RC oscillator frequency 22 42 kHz Embedded low power RC oscillator (SLCK) 264
ERASE pin minimum high time to reinitialize Flash 220 ms ERASE pin held high to perform Flash reinitialization 27
Operating temperature range (industrial) -40 85 C Industrial grade, ATSAM3U2CA-AU LQFP100 per ordering information 1137
PIO internal pull-up resistor 100 kOhm Typical pull-up for all I/Os 25
On-die termination series resistor 36 Ohm Typical ODT on PIO driver output 25
NRST internal pull-up resistor NRST 100 kOhm Permanent pull-up to VDDIO 26
NRSTB internal pull-up resistor NRSTB 15 kOhm Permanent pull-up 26
TST internal pull-down resistor TST 15 kOhm Permanent pull-down to GND 26
JTAGSEL internal pull-down resistor JTAGSEL 15 kOhm Permanent pull-down to GNDBU 26
ERASE internal pull-down resistor ERASE 15 kOhm Permanent pull-down to GND 26

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the 134

CAD (KiCad official)

  • Symbol: ATSAM3U2CA-AU
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: atsam3u2ca-au-etched.step / atsam3u2ca-au-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsam3u2ca-au.step / atsam3u2ca-au.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1163 pp, sha256 b84d00c06a823c14, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF