component

ATMEGA808-MF

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Microchip Tech Pre-ordered MCUs, VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatmega808-mffactory-2.0.0extractor-text

Verified ATMEGA808-MF

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATMEGA808-MF · VQFN-32(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 552-page datasheet
  • ✓distributor: lcsc C1340515, digikey ATMEGA808-MF-ND, mouser 556-ATMEGA808-MF
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-qtwhttjl/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.532)
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ atmega808-mf.kicad_sym✓ atmega808-mf.kicad_mod✓ atmega808-mf.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers atmega808-mf: viewers · Ray 5d ago
atmega808-mf-etched.glb Publish 0.1.0 · Ray 5d ago
atmega808-mf-etched.step atmega808-mf: factory component page (tier=mfr) · Ray 5d ago
atmega808-mf-hero.glb atmega808-mf: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
atmega808-mf-hero.overlay.json Publish 0.1.0 · Ray 5d ago
atmega808-mf.glb Publish 0.1.0 · Ray 5d ago
atmega808-mf.kicad_mod Publish 0.1.0 · Ray 5d ago
atmega808-mf.kicad_sym Publish 0.1.0 · Ray 5d ago
atmega808-mf.lbr Publish 0.1.0 · Ray 5d ago
atmega808-mf.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
verification.json Verified: Published by the parts factory: tier mfr, 33 pins · Ray 5d ago

ATMEGA808-MF

Microchip Tech · Pre-ordered MCUs · VQFN-32(5x5)

ATMEGA808-MF from Microchip Tech, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA3 bidirectional GPIO pin PA3 on the VDD power domain, with alternate functions TWI0 SCL (host), USART0 XDIR, TCA0 WO3 and CCL LUT0 OUT per the multiplexing table.
2 PA4 bidirectional GPIO pin PA4 on the VDD power domain, with alternate functions USART0 TxD (alternate position), SPI0 MOSI and TCA0 WO4.
3 PA5 bidirectional GPIO pin PA5 on the VDD power domain, with alternate functions USART0 RxD (alternate position), SPI0 MISO and TCA0 WO5.
4 PA6 bidirectional GPIO pin PA6 on the VDD power domain, with alternate functions USART0 XCK (alternate position), SPI0 SCK and CCL LUT0 OUT (alternate position).
5 PA7 bidirectional GPIO pin PA7 on the VDD power domain, with alternate functions CLKOUT, AC0 OUT, USART0 XDIR (alternate position), SPI0 SS and EVSYS EVOUTA (alternate position).
6 PC0 bidirectional GPIO pin PC0 on the VDD power domain, with alternate functions USART1 TxD, SPI0 MOSI (alternate position), TCA0 WO0 (alternate position), TCB2 WO (alternate position) and CCL LUT1 IN0.
7 PC1 bidirectional GPIO pin PC1 on the VDD power domain, with alternate functions USART1 RxD, SPI0 MISO (alternate position), TCA0 WO1 (alternate position), TCB3 WO (alternate position) and CCL LUT1 IN1.
8 PC2 bidirectional GPIO pin PC2 on the VDD power domain, with alternate functions TWI0 SDA (host, alternate position), USART1 XCK, SPI0 SCK (alternate position), TCA0 WO2 (alternate position), EVSYS EVOUTC and CCL LUT1 IN2.
9 PC3 bidirectional GPIO pin PC3 on the VDD power domain, with alternate functions TWI0 SCL (host, alternate position), USART1 XDIR, SPI0 SS (alternate position), TCA0 WO3 (alternate position) and CCL LUT1 OUT.
10 PD0 bidirectional GPIO pin PD0 on the VDD power domain, with analog input AIN0, TCA0 WO0 (alternate position) and CCL LUT2 IN0.
11 PD1 bidirectional GPIO pin PD1 on the VDD power domain, with analog input AIN1, TCA0 WO1 (alternate position) and CCL LUT2 IN1.
12 PD2 bidirectional GPIO pin PD2 on the VDD power domain, with analog input AIN2, TCA0 WO2 (alternate position), EVSYS EVOUTD and CCL LUT2 IN2.
13 PD3 bidirectional GPIO pin PD3 on the VDD power domain, with analog input AIN3, AC0 N0, TCA0 WO3 (alternate position) and CCL LUT2 OUT.
14 PD4 bidirectional GPIO pin PD4 on the VDD power domain, with analog input AIN4, AC0 P1 and TCA0 WO4 (alternate position).
15 PD5 bidirectional GPIO pin PD5 on the VDD power domain, with analog input AIN5, AC0 N1 and TCA0 WO5 (alternate position).
16 PD6 bidirectional GPIO pin PD6 on the VDD power domain, with analog input AIN6, AC0 P2 and CCL LUT2 OUT (alternate position).
17 PD7 bidirectional GPIO pin PD7 on the VDD power domain, with analog input AIN7, AC0 N2, VREFA (external voltage reference) and EVSYS EVOUTD (alternate position).
18 AVDD power_in Analog supply pin for the AVDD power domain, which feeds the GPIO on AVDD power domain and the analog functions.
19 GND power_in Ground reference pin for the device.
20 PF0 (TOSC1) bidirectional GPIO pin PF0 on the VDD power domain, which is also the TOSC1 clock/crystal connection, with USART2 TxD, TCA0 WO0 (alternate position) and CCL LUT3 IN0.
21 PF1 (TOSC2) bidirectional GPIO pin PF1 on the VDD power domain, which is also the TOSC2 clock/crystal connection, with USART2 RxD, TCA0 WO1 (alternate position) and CCL LUT3 IN1.
22 PF2 bidirectional GPIO pin PF2 on the VDD power domain, with TWI0 SDA (client, alternate position), analog input AIN12, USART2 XCK, TCA0 WO2 (alternate position), EVSYS EVOUTF and CCL LUT3 IN2.
23 PF3 bidirectional GPIO pin PF3 on the VDD power domain, with TWI0 SCL (client, alternate position), analog input AIN13, USART2 XDIR, TCA0 WO3 (alternate position) and CCL LUT3 OUT.
24 PF4 bidirectional GPIO pin PF4 on the VDD power domain, with analog input AIN14, USART2 TxD (alternate position), TCA0 WO4 (alternate position) and TCB0 WO (alternate position).
25 PF5 bidirectional GPIO pin PF5 on the VDD power domain, with analog input AIN15, USART2 RxD (alternate position), TCA0 WO5 (alternate position) and TCB1 WO (alternate position).
26 PF6 (RESET) bidirectional GPIO pin PF6 on the VDD power domain, which can be configured as the RESET pin via the RSTPINCFG fuse, with USART2 XCK (alternate position) and CCL LUT3 OUT (alternate position).
27 UPDI bidirectional Unified Program and Debug Interface pin used for programming and debugging the device.
28 VDD power_in Supply pin for the VDD power domain; the datasheet gives a device supply voltage of 1.8-5.5 V.
29 GND power_in Ground reference pin for the device.
30 PA0 (EXTCLK) bidirectional GPIO pin PA0 on the VDD power domain, which is also the EXTCLK external clock input, with USART0 TxD, TCA0 WO0 (alternate position) and CCL LUT0 IN0.
31 PA1 bidirectional GPIO pin PA1 on the VDD power domain, with USART0 RxD, TCA0 WO1 and CCL LUT0 IN1.
32 PA2 bidirectional GPIO pin PA2 on the VDD power domain, with TWI0 SDA (host), USART0 XCK, TCA0 WO2, TCB0 WO (alternate position), EVSYS EVOUTA and CCL LUT0 IN2.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-32(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage 1.8 5.5 V 520
Temperature Range (ATmega808-MF, -40°C to +125°C grade) -40 125 °C 520
Max. CPU Speed 20 MHz 520

CAD (KiCad official)

  • Symbol: ATMEGA808-MF
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: atmega808-mf-etched.step / atmega808-mf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atmega808-mf.step / atmega808-mf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (552 pp, sha256 e4bbeee766cda6b4, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF