ATF1502ASL-25AU44 from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	I/O/TDI	bidirectional	I/O pin (macrocell 4) that serves as JTAG TDI for boundary-scan/ISP when JTAG is enabled, with optional pull-up.
2	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 5) with programmable pin-keeper and slew rate.
3	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 6) with programmable pin-keeper and slew rate.
4	GND	power_in	Ground pin.
5	PD1/I/O	bidirectional	I/O pin that can act as power-down pin PD1; when high with power-down enabled, supply current drops below 5mA and the pin cannot be used as logic input or output.
6	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 8) with programmable pin-keeper and slew rate.
7	I/O/TMS	bidirectional	I/O pin (macrocell 9) that serves as JTAG TMS for boundary-scan/ISP when JTAG is enabled, with optional pull-up.
8	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 10) with programmable pin-keeper and slew rate.
9	VCC	power_in	Device supply pin, +5V (5V ±5% commercial, ±10% industrial).
10	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 11) with programmable pin-keeper and slew rate.
11	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 12) with programmable pin-keeper and slew rate.
12	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 13) with programmable pin-keeper and slew rate.
13	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 14) with programmable pin-keeper and slew rate.
14	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 15) with programmable pin-keeper and slew rate.
15	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 16) with programmable pin-keeper and slew rate.
16	GND	power_in	Ground pin.
17	VCC	power_in	Device supply pin, +5V (5V ±5% commercial, ±10% industrial).
18	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 32) with programmable pin-keeper and slew rate.
19	PD2/I/O	bidirectional	I/O pin that can act as power-down pin PD2; when high with power-down enabled, supply current drops below 5mA and the pin cannot be used as logic input or output.
20	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 30) with programmable pin-keeper and slew rate.
21	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 29) with programmable pin-keeper and slew rate.
22	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 28) with programmable pin-keeper and slew rate.
23	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 27) with programmable pin-keeper and slew rate.
24	GND	power_in	Ground pin.
25	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 26) with programmable pin-keeper and slew rate.
26	I/O/TCK	bidirectional	I/O pin (macrocell 25) that serves as JTAG TCK for boundary-scan/ISP when JTAG is enabled.
27	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 24) with programmable pin-keeper and slew rate.
28	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 23) with programmable pin-keeper and slew rate.
29	VCC	power_in	Device supply pin, +5V (5V ±5% commercial, ±10% industrial).
30	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 22) with programmable pin-keeper and slew rate.
31	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 21) with programmable pin-keeper and slew rate.
32	I/O/TDO	bidirectional	I/O pin (macrocell 20) that serves as JTAG TDO for boundary-scan/ISP when JTAG is enabled.
33	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 19) with programmable pin-keeper and slew rate.
34	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 18) with programmable pin-keeper and slew rate.
35	GCLK3/I/O	bidirectional	I/O pin (macrocell 32 per block diagram) that can also serve as global clock input GCLK3.
36	GND	power_in	Ground pin.
37	GCLK1/I	input	Dedicated input that can serve as global clock GCLK1 or general logic input.
38	OE1/I	input	Dedicated input that can serve as global output enable OE1 or general logic input.
39	GCLR/I	input	Dedicated input that can serve as global clear (register reset) or general logic input.
40	GCLK2/OE2/I	input	Dedicated input that can serve as global clock GCLK2, global output enable OE2, or general logic input.
41	VCC	power_in	Device supply pin, +5V (5V ±5% commercial, ±10% industrial).
42	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 1) with programmable pin-keeper and slew rate.
43	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 2) with programmable pin-keeper and slew rate.
44	I/O	bidirectional	General-purpose bidirectional I/O pin (macrocell 3) with programmable pin-keeper and slew rate.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	TQFP-44(10x10)
Category	Embedded Processors & Controllers
Pins	44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VCC (5.0V) Power Supply	VCC	-10		10	%	Industrial, 5.0V nominal	10
Operating Temperature (Ambient)		-40		85	C	Industrial	10
Temperature Under Bias		-40		85	C		10
Storage Temperature		-65		150	C		10
Voltage on Any Pin with Respect to Ground		-2		7	V	See note 1	10
Voltage on Input Pins with Respect to Ground During Programming		-2		14	V	See note 1	10
Programming Voltage with Respect to Ground		-2		14	V	See note 1	10
Input Pin Capacitance	CIN		8	10	pF	VIN = 0V; f = 1MHz	10
I/O Pin Capacitance	CI/O		8	10	pF	VOUT = 0V; f = 1MHz	10
Input or I/O Low Leakage Current	IIL		-2	-10	μA	VIN = VCC	11
Input or I/O High Leakage Current	IIH		2	10	μA		11
Tri-state Output Off-state Current	IOZ	-40		40	μA	VO = VCC or GND	11
Power Supply Current, Standby (L mode)	ICC1			10	μA	VCC = Max; VIN = 0, VCC; L Mode; Ind.	11
Power Supply Current, Power-down Mode	ICC2		1	5	mA	VCC = Max; VIN = 0, VCC; PD Mode	11
Reduced-power Mode Supply Current, Standby	ICC3			40	mA	VCC = Max; VIN = 0, VCC; Std Mode; Ind.	11
Input Low Voltage	VIL	-0.3		0.8	V		11
Input High Voltage	VIH	2			V		11
Output Low Voltage (TTL)	VOL			0.45	V	VIN = VIH or VIL; VCC = Min, IOL = 12mA; Ind.	11
Output Low Voltage (CMOS)	VOL			0.2	V	VIN = VIH or VIL; VCC = Min, IOL = 0.1mA; Ind.	11
Output High Voltage (TTL)	VOH	2.4			V	VIN = VIH or VIL; VCC = Min, IOH = -4.0mA	11
Input or Feedback to Non-registered Output	tPD1			25	ns		12
I/O Input or Feedback to Non-registered Feedback	tPD2			25	ns		12
Global Clock Setup Time	tSU			20	ns		12
Global Clock Hold Time	tH			0	ns		12
Global Clock Setup Time of Fast Input	tFSU			5	ns		12
Global Clock Hold Time of Fast Input	tFH			2	MHz		12
Global Clock to Output Delay	tCOP			13	ns		12
Global Clock High Time	tCH			7	ns		12
Global Clock Low Time	tCL			7	ns		12
Array Clock Setup Time	tASU			5	ns		12
Array Clock Hold Time	tAH			6	ns		12
Array Clock Output Delay	tACOP			25	ns		12
Array Clock High Time	tACH			10	ns		12
Array Clock Low Time	tACL			10	ns		12
Minimum Clock Global Period	tCNT			22	ns		12
Maximum Internal Global Clock Frequency	fCNT			50	MHz		12
Minimum Array Clock Period	tACNT			22	ns		12
Maximum Internal Array Clock Frequency	fACNT			50	MHz		12
Maximum Clock Frequency	fMAX			60	MHz		12
Input Pad and Buffer Delay	tIN			2	ns		12
I/O Input Pad and Buffer Delay	tIO			2	ns		12
Fast Input Delay	tFIN			2	ns		12
Foldback Term Delay	tSEXP			12	ns		12
Cascade Logic Delay	tPEXP			2	ns		12
Logic Array Delay	tLAD			8	ns		12
Logic Control Delay	tLAC			8	ns		12
Internal Output Enable Delay	tIOE			4	ns		12
Output Buffer and Pad Delay	tOD1			6	ns	Slow slew rate = OFF; VCC = 5.0V; CL = 35pF	12
Output Buffer Enable Delay	tZX1			10	ns	Slow slew rate = OFF; VCCIO = 5.0V; CL = 35pF	13
Output Buffer Enable Delay	tZX3			12	ns	Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35pF	13
Output Buffer Disable Delay	tXZ			8	ns	CL = 5pF	13
Register Setup Time	tSU			6	ns		13
Register Hold Time	tH			6	ns		13
Register Setup Time of Fast Input	tFSU			3	ns		13
Register Hold Time of Fast Input	tFH			5	ns		13
Array Clock Delay	tIC			8	ns		13
Register Enable Time	tEN			8	ns		13
Register Clear Time	tCLR			6	ns		13
Reduced-power Adder	tRPA			15	ns		13

CAD (KiCad official)

Symbol: ATF1502ASL-25AU44
Footprint: Package_QFP:TQFP-44_10x10mm_P0.8mm
3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
3D model files: atf1502asl-25au44-etched.step / atf1502asl-25au44-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atf1502asl-25au44.step / atf1502asl-25au44.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (29 pp, sha256 1abab0d93d034ad0, retrieved 2026-11-07, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ATF1502ASL-25AU44

Verified ATF1502ASL-25AU44

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README