component

AT45DB041E-SHN-B

Public Made by Adom

by adom

Adesto Technologies Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsat45db041e-shn-bfactory-2.0.0extractor-text

Verified AT45DB041E-SHN-B

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AT45DB041E-SHN-B · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 70-page datasheet
  • ✓distributor: lcsc C1348793, digikey 1265-1066-5-ND, mouser 988-AT45DB041E-SHN-B
  • ✓family: SOIC-8_5.3x5.3mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-d4n81mf0/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.66)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ at45db041e-shn-b.kicad_sym✓ at45db041e-shn-b.kicad_mod✓ at45db041e-shn-b.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
at45db041e-shn-b / README.md
History Download
Ray Publish 0.1.0 ca53d88 5d ago

AT45DB041E-SHN-B

Adesto Technologies · Pre-ordered Chips · SOIC-8

AT45DB041E-SHN-B from Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SI input Serial Input: shifts in all commands, addresses and data, latched on the rising edge of SCK and ignored while the device is deselected.
2 SCK input Serial Clock: controls data flow, with input latched on the rising edge and output on SO clocked out on the falling edge of SCK.
3 RESET input Active-low reset: a low level terminates the operation in progress and holds the internal state machine idle; drive high externally if unused.
4 CS input Active-low Chip Select: asserting selects the device, deasserting deselects it into standby (not Deep Power-Down) and puts SO in high-impedance.
5 WP input Active-low Write Protect: protects sectors set in the Sector Protection Register against program/erase; internally pulled high, may float if unused but connecting to VCC is recommended.
6 VCC power_in Device power supply, 1.65V to 3.6V; operation at invalid VCC voltages may produce spurious results.
7 GND power_in Ground reference for the power supply, to be connected to system ground.
8 SO tri_state Serial Output: shifts data out on the falling edge of SCK and is high-impedance whenever the device is deselected.

Key specifications

Parameter Value
Manufacturer Adesto Technologies
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ultra-Deep Power-Down Current IUDPD 0.4 1 µA CS= VCC. All other inputs at 0V or VCC 47
Deep Power-Down Current IDPD 4.5 12 µA CS= VCC. All other inputs at 0V or VCC 47
Standby Current ISB 25 40 µA CS= VCC. All other inputs at 0V or VCC 47
Active Current, Low Power Read (01h) Operation ICC1 6 9 mA f = 1MHz; IOUT = 0mA 47
Active Current, Low Power Read (01h) Operation ICC1 7 10 mA f = 15MHz; IOUT = 0mA 47
Active Current, Read Operation ICC2 10 12 mA f = 50MHz; IOUT = 0mA 47
Active Current, Read Operation ICC2 12 15 mA f = 85MHz; IOUT = 0mA 47
Active Current, Program Operation ICC3 14 16 mA CS=VCC 47
Active Current, Erase Operation ICC4 8 12 mA CS=VCC 47
Input Load Current ILI 1 µA All inputs at CMOS levels 47
Output Leakage Current ILO 1 µA All inputs at CMOS levels 47
Output Low Voltage VOL 0.4 V IOL = 100µA 47
SCK Frequency fSCK 70 MHz 1.65V to 3.6V 48
SCK Frequency for Continuous Read (0x0B) fCAR1 70 MHz 1.65V to 3.6V 48
SCK Frequency for Continuous Read (0x03) (Low Frequency) fCAR2 40 MHz 1.65V to 3.6V 48
SCK Frequency for Continuous Read (Low Power Mode, 01h Opcode) fCAR3 15 MHz 1.65V to 3.6V 48
SCK Frequency for Continuous Read (0x1B) fCAR4 85 MHz 1.65V to 3.6V 48
SCK High Time tWH 4 ns 1.65V to 3.6V 48
SCK Low Time tWL 4 ns 1.65V to 3.6V 48
SCK Rise Time, Peak-to-peak tSCKR 0.1 V/ns 1.65V to 3.6V 48
SCK Fall Time, Peak-to-peak tSCKF 0.1 V/ns 1.65V to 3.6V 48
Minimum CS High Time tCS 20 ns 1.65V to 3.6V 48
CS Setup Time tCSS 6 ns 1.65V to 3.6V 48
CS Hold Time tCSH 5 ns 1.65V to 3.6V 48
Data In Setup Time tSU 2 ns 1.65V to 3.6V 48
Data In Hold Time tH 1 ns 1.65V to 3.6V 48
Output Hold Time tHO 0 ns 1.65V to 3.6V 48
Output Disable Time tDIS 8 ns 1.65V to 3.6V 48
Output Valid tV 7 ns 1.65V to 3.6V 48
WP Low to Protection Enabled tWPE 1 µs 1.65V to 3.6V 48
WP High to Protection Disabled tWPD 1 µs 1.65V to 3.6V 48
Freeze Sector Lockdown Time (from CS High) tLOCK 200 µs 1.65V to 3.6V 48
CS High to Ultra-Deep Power-Down tEUDPD 3 µs 1.65V to 3.6V 48
Minimum CS Low Time to Exit Ultra-Deep Power-Down tCSLU 20 ns 1.65V to 3.6V 48
Exit Ultra-Deep Power-Down Time tXUDPD 280 µs 1.65V to 3.6V 48
CS High to Deep Power-Down tEDPD 2 µs 1.65V to 3.6V 48
Resume from Deep Power-Down Time tRDPD 35 µs 1.65V to 3.6V 48
Page to Buffer Transfer Time tXFR 100 µs 1.65V to 3.6V 48
RESET Pulse Width tRST 10 µs 1.65V to 3.6V 48
RESET Recovery Time tREC 1 µs 1.65V to 3.6V 48
Software Reset Time tSWRST 35 µs 1.65V to 3.6V 48
Page Erase and Programming Time (256/264 bytes) tEP 10 25 ms 1.65V to 3.6V 49
Page Programming Time tP 1.5 3 ms 1.65V to 3.6V 49
Byte Programming Time tBP 8 µs 1.65V to 3.6V 49
Page Erase Time tPE 12 25 ms 1.65V to 3.6V 49
Block Erase Time tBE 30 35 ms 1.65V to 3.6V 49
Sector Erase Time tSE 0.7 1.1 s 1.65V to 3.6V 49
Chip Erase Time tCE 6 17 s 1.65V to 3.6V 49
Suspend Time, Program tSUSP 8 15 µs 1.65V to 3.6V 49
Suspend Time, Erase tSUSP 20 30 µs 1.65V to 3.6V 49
Resume Time, Program tRES 8 15 µs 1.65V to 3.6V 49
Resume Time, Erase tRES 20 30 µs 1.65V to 3.6V 49
OTP Security Register Program Time tOTPP 200 500 µs 1.65V to 3.6V 49
All Output Voltages with Respect to Ground -0.6 4.2 V Max VCC of 3.6V + 0.6V 46
All Input Voltages with Respect to Ground (excluding VCC pin, including NC pins) -0.6 4.2 V Max VCC of 3.6V + 0.6V 46
Storage Temperature -65 150 C 46
Temperature under Bias -55 125 C 46
VCC Power Supply VCC 1.65 3.6 V 46
Operating Temperature (Case) Industrial -40 85 C 46

CAD (KiCad official)

  • Symbol: AT45DB041E-SHN-B
  • Footprint: Package_SO:SOIC-8_5.3x5.3mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at45db041e-shn-b-etched.step / at45db041e-shn-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at45db041e-shn-b.step / at45db041e-shn-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Adesto Technologies datasheet (70 pp, sha256 c630b496f0a3c17a, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF