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AT45DB021E-SSHN-B

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Adesto Technologies Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT45DB021E-SSHN-B

Adesto Technologies · Pre-ordered Chips · SOIC-8

AT45DB021E-SSHN-B from Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SI input Serial Input: shifts in all command, address and data bits, latched on the rising edge of SCK and ignored when the device is deselected (CS high).
2 SCK input Serial Clock: controls data flow, with input latched on the rising edge and SO output clocked out on the falling edge of SCK.
3 RESET input Active-low reset: a low level terminates the operation in progress and resets the internal state machine to idle; drive high externally if unused (internal power-on reset, no power-on restrictions).
4 CS input Active-low Chip Select: asserting selects the device, a high-to-low transition starts an operation, and when deasserted the device is deselected (standby) and SO is high-impedance.
5 WP input Active-low Write Protect: when asserted, sectors specified in the Sector Protection Register are protected against program and erase; internally pulled high, may be left floating if unused but recommended to be tied to VCC.
6 VCC power_in Device power supply (1.65V to 3.6V); operation at invalid VCC voltages may produce spurious results.
7 GND power_in Ground reference for the power supply, to be connected to system ground.
8 SO output Serial Output: shifts data out on the falling edge of SCK and is high-impedance whenever the device is deselected (CS high).

Key specifications

Parameter Value
Manufacturer Adesto Technologies
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Temperature under bias -55 125 °C 44
Storage temperature -65 150 °C 44
All input voltages (except VCC, including NC pins) w.r.t. ground -0.6 6.25 V 44
All output voltages w.r.t. ground -0.6 V Upper limit printed as VCC + 0.6V 44
Operating temperature (case), Industrial -40 85 °C 44
VCC power supply VCC 1.65 3.6 V 44
Ultra-Deep Power-Down current IUDPD 0.2 1 µA CS= VCC. All other inputs at 0V or VCC 45
Deep Power-Down current IDPD 4.5 12 µA CS= VCC. All other inputs at 0V or VCC 45
Standby current ISB 25 40 µA CS= VCC. All other inputs at 0V or VCC 45
Active current, low power read (01h) ICC1 6 9 mA f = 1MHz; IOUT = 0mA 45
Active current, low power read (01h) ICC1 7 10 mA f = 15MHz; IOUT = 0mA 45
Active current, read operation ICC2 10 12 mA f = 50MHz; IOUT = 0mA 45
Active current, read operation ICC2 12 15 mA f = 85MHz; IOUT = 0mA 45
Active current, program operation ICC3 10 12 mA CS = VCC 45
Active current, erase operation ICC4 8 12 mA CS = VCC 45
Input load current ILI 1 µA All inputs at CMOS levels 45
Output leakage current ILO 1 µA All inputs at CMOS levels 45
Output low voltage VOL 0.2 V IOL = 100µA 45
SCK frequency fSCK 70 MHz 45
SCK frequency for continuous read fCAR1 70 MHz 45
SCK frequency for continuous read (low frequency) fCAR2 33 MHz 45
SCK frequency for continuous read (low power mode, 01h) fCAR3 15 MHz 46
SCK high time tWH 4 ns 46
SCK low time tWL 4 ns 46
SCK rise time, peak-to-peak tSCKR 0.1 V/ns Based on characterization, not 100% tested 46
SCK fall time, peak-to-peak tSCKF 0.1 V/ns Based on characterization, not 100% tested 46
Minimum CS high time tCS 20 ns 46
CS setup time tCSS 6 ns 46
CS hold time tCSH 5 ns 46
Data in setup time tSU 2 ns 46
Data in hold time tH 1 ns 46
Output hold time tHO 0 ns 46
Output disable time tDIS 8 ns Based on characterization, not 100% tested 46
Output valid tV 7 ns 46
WP low to protection enabled tWPE 1 µs 46
WP high to protection disabled tWPD 1 µs 46
Freeze sector lockdown time (from CS high) tLOCK 200 µs 46
CS high to Ultra-Deep Power-Down tEUDPD 3 µs Based on characterization, not 100% tested 46
Minimum CS low time to exit Ultra-Deep Power-Down tCSLU 20 ns 46
Exit Ultra-Deep Power-Down time tXUDPD 240 µs 46
CS high to Deep Power-Down tEDPD 2 µs Based on characterization, not 100% tested 46
Resume from Deep Power-Down time tRDPD 35 µs 46
Page to buffer transfer time tXFR 100 µs 46
Page to buffer compare time tCOMP 100 µs 46
RESET pulse width tRST 10 µs 46
RESET recovery time tREC 1 µs 46
Software reset time tSWRST 35 µs 46
Page erase and programming time (256/264 bytes) tEP 10 35 ms 47
Page programming time tP 1.5 3 ms 47
Byte programming time tBP 8 µs 47
Page erase time tPE 6 25 ms 47
Block erase time tBE 25 35 ms 47
Sector erase time tSE 350 550 ms 47
Chip erase time tCE 3 4 s 47
OTP security register program time tOTPP 200 500 µs 47

CAD (KiCad official)

  • Symbol: AT45DB021E-SSHN-B
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at45db021e-sshn-b-etched.step / at45db021e-sshn-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at45db021e-sshn-b.step / at45db021e-sshn-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Adesto Technologies datasheet (68 pp, sha256 db6fabc37825965c, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF