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AT25DF021A-SSHN-T

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Adesto Technologies NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmemoryat25df021a-sshn-tfactory-2.0.0extractor-text

Verified AT25DF021A-SSHN-T

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AT25DF021A-SSHN-T · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 51-page datasheet
  • ✓distributor: lcsc C2061548, digikey 1265-1163-2-ND, mouser 988-AT25DF021ASSHNT
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-qi2vnwvp/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ at25df021a-sshn-t.kicad_sym✓ at25df021a-sshn-t.kicad_mod✓ at25df021a-sshn-t.step
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AT25DF021A-SSHN-T

Adesto Technologies · NOR FLASH · SOIC-8

AT25DF021A-SSHN-T from Adesto Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip select, active low: asserting CS selects the device, deasserting it deselects the device into standby (not Deep Power-Down) with SO high-impedance, and a high-to-low transition starts an operation.
2 SO (I/O1) bidirectional Serial output clocked out on the falling edge of SCK, becoming I/O1 during Dual-Output Read, and held in high-impedance whenever CS is deasserted.
3 WP input Write protect input controlling the hardware locking feature; internally pulled high and recommended to be externally connected to VCC whenever possible.
4 GND power_in Ground reference for the power supply; should be connected to the system ground.
5 SI (I/O0) bidirectional Serial input for all data, command and address input, latched on the rising edge of SCK, becoming I/O0 during Dual-Output Read and ignored when the device is deselected.
6 SCK input Serial clock: SI is latched on the rising edge of SCK and SO is clocked out on the falling edge of SCK.
7 HOLD input Pauses serial communication while asserted (CS asserted and SCK low to start); SCK and SI transitions are ignored and SO is high-impedance; internally pulled high.
8 VCC power_in Device power supply; operations at invalid VCC voltages may produce spurious results and should not be attempted (supply range 1.65V to 3.6V).

Key specifications

Parameter Value
Manufacturer Adesto Technologies
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ultra-Deep Power-Down Current IUDPD 0.2 0.6 µA CS = VCC. All other inputs at 0V or VCC 38
Deep Power-Down Current IDPD 4.5 15 µA CS = VCC. All other inputs at 0V or VCC 38
Standby Current ISB 25 40 µA CS = VCC. All other inputs at 0V or VCC 38
Active Current, Low Power Read (03h, 0Bh) ICC1 4.5 6 mA f = 1MHz; IOUT = 0mA 38
Active Current, Low Power Read (03h, 0Bh) ICC1 5 7 mA f = 20MHz; IOUT = 0mA 38
Active Current, Read Operation ICC2 5 7 mA f = 50MHz; IOUT = 0mA 38
Active Current, Program Operation ICC3 11 14 mA CS = VCC 38
Active Current, Erase Operation ICC4 11 14 mA CS = VCC 38
Input Load Current ILI 1 µA All inputs at CMOS levels 38
Output Leakage Current ILO 1 µA All inputs at CMOS levels 38
Output Low Voltage VOL 0.2 0.4 V IOL = 100µA 38
Maximum Clock Frequency for All Operations (including 0Bh opcode) fCLK 104 MHz 39
Maximum Clock Frequency for 03h Opcode (Read Array, Low Frequency) fRDLF 25 MHz 39
Maximum Clock Frequency for 3B Opcode fRDDO 50 MHz 39
Clock High Time tCLKH 4.5 ns 39
Clock Low Time tCLKL 4 ns 39
Chip Select High Time tCSH 35 ns 39
Chip Select Low Setup Time (relative to Clock) tCSLS 6 ns 39
Chip Select Low Hold Time (relative to Clock) tCSLH 6 ns 39
Chip Select High Setup Time (relative to Clock) tCSHS 6 ns 39
Chip Select High Hold Time (relative to Clock) tCSHH 6 ns 39
Data In Setup Time tDS 2 ns 39
Data In Hold Time tDH 1 ns 39
Output Disable Time tDIS 8 ns 39
Output Valid Time tV 7.5 ns 39
Output Hold Time tOH 0 ns 39
HOLD Low Setup Time (relative to Clock) tHLS 6 ns 39
HOLD Low Hold Time (relative to Clock) tHLH 6 ns 39
HOLD High Setup Time (relative to Clock) tHHS 6 ns 39
HOLD High Hold Time (relative to Clock) tHHH 6 ns 39
HOLD Low to Output High-Z tHLQZ 7 ns 39
HOLD High to Output Low-Z tHHQX 7 ns 39
Write Protect Setup Time tWPS 20 ns 39
Write Protect Hold Time tWPH 100 ns 39
Chip Select High to Deep Power-Down tEDPD 3 µs 39
Chip Select High to Ultra Deep Power-Down tEUDPD 3 µs 40
Software Reset Time tSWRST 40 µs 40
Minimum Chip Select Low to Exit Ultra Deep Power-Down tCSLU 20 ns 40
Exit Ultra Deep Power-Down Time tXUDPD 70 µs 40
Chip Select High to Standby Mode tRDPD 8 µs 40
Page Program Time 256 Bytes tPP 1.25 2.5 ms 40
Page Erase Time 256 Bytes tPE 6 20 ms 40
Block Erase Time 4 Kbytes tBLKE 40 60 ms 40
Block Erase Time 32 Kbytes tBLKE 250 500 ms 40
Block Erase Time 64 Kbytes tBLKE 500 1000 ms 40
Chip Erase Time tCHPE 2 4 sec 40
OTP Security Register Program Time tOTPP 400 950 µs 40
VCC for device initialization VPWD 1 V 41
Minimum duration for device initialization tPWD 300 µs 41
Minimum VCC to chip select low time for Read command tVCSL 70 µs 41
VCC rise time tVR 1 500000 µs/V 41
Power on reset voltage VPOR 1.45 1.6 V 41
Power up delay time before Program or Erase is allowed tPUW 3 ms 41
Temperature under Bias -55 125 °C 37
Storage Temperature -65 150 °C 37
All Input Voltages (including NC Pins) with Respect to Ground -0.6 4.1 V 37
Operating Temperature (Case) Industrial -40 85 °C 37
VCC Power Supply VCC 1.65 3.6 V 37

CAD (KiCad official)

  • Symbol: AT25DF021A-SSHN-T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: at25df021a-sshn-t-etched.step / at25df021a-sshn-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at25df021a-sshn-t.step / at25df021a-sshn-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Adesto Technologies datasheet (51 pp, sha256 02b96d961a99319b, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF