AT25128B-SSHL-T

{
  "schema_version": 1,
  "type": "component",
  "slug": "at25128b-sshl-t",
  "title": "AT25128B-SSHL-T",
  "brief": "Microchip EEPROM, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "memory",
    "at25128b-sshl-t"
  ],
  "component": {
    "mpn": "AT25128B-SSHL-T",
    "manufacturer": "Microchip",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Memory",
    "subcategory": "EEPROM",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/07940475b493401e936fe9aa4c453984.pdf",
    "parts": {
      "symbol": "at25128b-sshl-t.kicad_sym",
      "footprint": "at25128b-sshl-t.kicad_mod",
      "model_3d": "at25128b-sshl-t-etched.glb",
      "model_3d_plain": "at25128b-sshl-t.glb",
      "model_3d_step": "at25128b-sshl-t-etched.step",
      "model_3d_step_plain": "at25128b-sshl-t.step",
      "lbr": "at25128b-sshl-t.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "CS",
        "type": "input",
        "description": "Active-low SPI Chip Select. Pulling CS low selects the device and starts a serial transaction; the first byte after the falling edge is interpreted as the opcode. Bringing CS high ends the transaction and, for WRITE, triggers the internal programming cycle."
      },
      {
        "number": "2",
        "name": "SO",
        "type": "output",
        "description": "SPI Serial Data Output (MISO). Data is shifted out on the falling edge of SCK, MSB first. The pin is high-impedance whenever CS is high or an invalid opcode is received."
      },
      {
        "number": "3",
        "name": "WP",
        "type": "input",
        "description": "Active-low hardware Write Protect. When WP is low and the WPEN bit in the status register is 1, writes to the status register (including BP0/BP1) are inhibited, providing hardware write protection. Held high for normal read/write."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Device ground reference for all supply and I/O signals."
      },
      {
        "number": "5",
        "name": "SI",
        "type": "input",
        "description": "SPI Serial Data Input (MOSI). Opcodes, addresses and write data are shifted in on the rising edge of SCK, MSB first."
      },
      {
        "number": "6",
        "name": "SCK",
        "type": "input",
        "description": "SPI Serial Clock input from the master. Supports SPI modes 0 (CPOL=0, CPHA=0) and 3 (CPOL=1, CPHA=1). Maximum 20 MHz at VCC = 4.5-5.5V, 10 MHz at 2.5-5.5V, 5 MHz at 1.8-5.5V."
      },
      {
        "number": "7",
        "name": "HOLD",
        "type": "input",
        "description": "Active-low Hold input. When taken low while SCK is low during a selected serial sequence, it pauses serial communication without resetting the transaction; SO becomes high-impedance and SI is ignored until HOLD is brought high again."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage, 1.8V to 5.5V. Full 20 MHz SCK operation requires VCC ≥ 4.5V; standby current is <5 µA at 5V with CS = VCC."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/07940475b493401e936fe9aa4c453984.pdf",
        "pages": 22,
        "sha256": "327b6418a5554831",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "at25128b-sshl-t.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "at25128b-sshl-t-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "77c2c3f84ccd6c06e5e19ce8b561f3e0b02c4afe2a5e9e3f804368c469edc7d3",
        "checked": "2026-11-03",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Microchip",
      "Package": "SOIC-8",
      "Category": "Memory",
      "Pins": "8"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "at25128b-sshl-t"
  ],
  "discovery_pitch": "AT25128B-SSHL-T (Microchip) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "at25128b-sshl-t.kicad_sym",
    "at25128b-sshl-t.kicad_mod",
    "at25128b-sshl-t.glb",
    "at25128b-sshl-t.step",
    "at25128b-sshl-t.lbr",
    "docs/hero.png",
    "docs/at25128b-sshl-t-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "at25128b-sshl-t-etched.step"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T17:10:33.335Z"
}