# AT24C512N

**HGSEMI** · EEPROM · DIP-8

AT24C512N from HGSEMI, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input hardwired to GND or VCC to set the device address (up to eight devices per bus); internally pulled down to GND if left floating. |
| 2 | A1 | input | Device address input hardwired to GND or VCC to set the device address (up to eight devices per bus); internally pulled down to GND if left floating. |
| 3 | NC | unconnected | No connect pin. |
| 4 | GND | power_in | Ground. |
| 5 | SDA | bidirectional | Serial data pin, bidirectional and open-drain driven, may be wire-ORed with other open-drain or open-collector devices, normally pulled high externally. |
| 6 | SCL | input | Serial clock input that positive-edge clocks data into and negative-edge clocks data out of the EEPROM. |
| 7 | WP | input | Write protect input: connected to GND allows normal write operations, connected to VCC inhibits all writes to the memory; internally pulled down to GND if left floating. |
| 8 | VCC | power_in | Power supply, VCC = 1.8V to 5.5V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | DIP-8 |
| Category | Memory |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage |  |  |  | 6.5 | V |  | 8 |
| Input / Output Voltage |  | -0.3 |  | 0.3 | V |  | 8 |
| Operating Ambient Temperature |  | -40 |  | 85 | ℃ |  | 8 |
| Storage Temperature |  | -65 |  | 150 | ℃ |  | 8 |
| Lead Temperature |  |  |  | 260 | ℃ | Soldering, 10 seconds | 8 |
| Operating Supply Voltage (recommended range) | VCC | 1.7 |  | 5.5 | V | TA = -40℃ to +85℃ | 8 |
| Supply Voltage | VCC1 | 1.8 |  | 5.5 | V |  | 8 |
| Supply Voltage | VCC2 | 2.5 |  | 5.5 | V |  | 8 |
| Supply Voltage | VCC3 | 2.7 |  | 5.5 | V |  | 8 |
| Supply Voltage | VCC4 | 4.5 |  | 5.5 | V |  | 8 |
| Supply Current | ICC1 |  | 0.4 | 1 | mA | VCC = 5.0V, READ at 400 kHz | 8 |
| Supply Current | ICC2 |  | 2 | 3 | mA | VCC = 5.0V, WRITE at 400 kHz | 8 |
| Standby Current | ISB1 |  | 0.6 | 1 | µA | VCC = 1.7V, VIN = VCC or VSS | 8 |
| Standby Current | ISB2 |  | 1 | 2 | µA | VCC = 2.5V, VIN = VCC or VSS | 8 |
| Standby Current | ISB4 |  | 1 | 5 | µA | VCC = 5.0V, VIN = VCC or VSS | 8 |
| Input Leakage Current | ILI |  | 0.1 | 3 | µA | VIN = VCC or VSS | 8 |
| Output Leakage Current | ILO |  | 0.05 | 3 | µA | VOUT = VCC or VSS | 8 |
| Input Low Level | VIL | -0.3 |  |  | V |  | 8 |
| Output Low Level | VOL3 |  |  | 0.4 | V | VCC = 5.0V, IOL = 3.0 mA | 8 |
| Output Low Level | VOL1 |  |  | 0.2 | V | VCC = 1.7V, IOL = 0.15 mA | 8 |
| Input/Output Capacitance (SDA) | CI/O |  |  | 8 | pF | VI/O = 0V | 8 |
| Input Capacitance (A0, A1, A2, SCL) | CIN |  |  | 6 | pF | VIN = 0V | 8 |
| Clock Frequency, SCL | fSCL |  |  | 400 | kHz | 1.7-volt column | 9 |
| Clock Frequency, SCL | fSCL |  |  | 1000 | kHz | 5.0-volt column | 9 |
| Clock Pulse Width Low | tLOW | 1.2 |  |  | µs | 1.7-volt column | 9 |
| Clock Pulse Width Low | tLOW | 0.6 |  |  | µs | 5.0-volt column | 9 |
| Clock Pulse Width High | tHIGH | 0.6 |  |  | µs | 1.7-volt column | 9 |
| Clock Pulse Width High | tHIGH | 0.4 |  |  | µs | 5.0-volt column | 9 |
| Noise Suppression Time | tI |  |  | 50 | ns | 1.7-volt column | 9 |
| Clock Low to Data Out Valid | tAA | 0.1 |  | 0.9 | µs | 1.7-volt column | 9 |
| Clock Low to Data Out Valid | tAA | 0.09 |  | 0.9 | µs | 5.0-volt column | 9 |
| Bus free time before a new transmission can start | tBUF | 1.2 |  |  | µs | 1.7-volt column | 9 |
| Bus free time before a new transmission can start | tBUF | 0.5 |  |  | µs | 5.0-volt column | 9 |
| Start Hold Time | tHD.STA | 0.6 |  |  | µs | 1.7-volt column | 9 |
| Start Hold Time | tHD.STA | 0.25 |  |  | µs | 5.0-volt column | 9 |
| Start Setup Time | tSU.STA | 0.6 |  |  | µs | 1.7-volt column | 9 |
| Start Setup Time | tSU.STA | 0.25 |  |  | µs | 5.0-volt column | 9 |
| Data In Hold Time | tHD.DAT | 0 | 0 |  | µs | 1.7-volt column | 9 |
| Data In Hold Time | tHD.DAT | 0 |  | 0 | µs | 5.0-volt column | 9 |
| Data In Setup Time | tSU.DAT | 100 | 0 |  | ns | 1.7-volt column | 9 |
| Data In Setup Time | tSU.DAT | 100 |  | 0 | ns | 5.0-volt column | 9 |
| Inputs Rise Time | tR |  |  | 0.3 | µs | 1.7-volt column | 9 |
| Inputs Fall Time | tF |  |  | 300 | ns | 1.7-volt column | 9 |
| Stop Setup Time | tSU.STO | 0.6 |  |  | µs | 1.7-volt column | 9 |
| Stop Setup Time | tSU.STO | 0.25 |  |  | µs | 5.0-volt column | 9 |
| Data Out Hold Time | tDH | 50 |  |  | ns | 1.7-volt column | 9 |
| Write Cycle Time | tWR |  | 5 | 5 | ms | 1.7-volt column | 9 |
| Write Cycle Time | tWR |  |  | 5 | ms | 5.0-volt column | 9 |

## CAD (KiCad official)

- Symbol: `AT24C512N`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files: `at24c512n-etched.step` / `at24c512n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at24c512n.step` / `at24c512n.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HGSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8756967473692860416) (14 pp, sha256 `39a46b933a720adf`, retrieved 2026-10-14, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/at24c512n-datasheet.pdf)