# AT24C128AN

**HGSEMI** · EEPROM · DIP-8

AT24C128AN from HGSEMI, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input, hard-wired; the A2/A1/A0 pins allow up to eight devices on one bus and float to logic low internally. |
| 2 | A1 | input | Device address input, hard-wired; the A2/A1/A0 pins allow up to eight devices on one bus and float to logic low internally. |
| 3 | A2 | input | Device address input, hard-wired; the A2/A1/A0 pins allow up to eight devices on one bus and float to logic low internally. |
| 4 | GND | power_in | Ground. |
| 5 | SDA | bidirectional | Bidirectional open-drain serial data pin that may be wire-ORed with other open-drain or open-collector devices and needs an external pull-up. |
| 6 | SCL | input | Serial clock input that clocks data in on the positive edge and out on the negative edge. |
| 7 | WP | input | Write protect: normal read/write when connected to GND, and the full 128K array is write-protected when connected to VCC. |
| 8 | VCC | power_in | Power supply, 1.7V to 5.5V operating range (absolute maximum -0.3V to +6.5V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | DIP-8 |
| Category | Memory |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage |  | -0.3 |  | 6.5 | V |  | 9 |
| Operating Ambient Temperature |  | -40 |  | 85 | ℃ |  | 9 |
| Storage Temperature |  | -65 |  | 150 | ℃ |  | 9 |
| Lead Temperature (Soldering) |  |  |  | 245 | ℃ | 10 seconds | 9 |
| Supply Voltage | VCC1 | 1.7 |  | 5.5 | V |  | 9 |
| Supply Voltage | VCC2 | 2.5 |  | 5.5 | V |  | 9 |
| Supply Voltage | VCC3 | 2.7 |  | 5.5 | V |  | 9 |
| Supply Voltage | VCC4 | 4.5 |  | 5.5 | V |  | 9 |
| Supply Current (READ) | ICC1 |  | 0.4 | 1 | mA | VCC=5.0V; READ at 400KHZ | 9 |
| Supply Current (WRITE) | ICC2 |  | 2 | 3 | mA | VCC=5.0V; WRITE at 400KHZ | 9 |
| Supply Current (standby) | ISB |  | 0.6 | 1 | μA | VCC=1.7V; VIN=VCC or VSS | 9 |
| Supply Current (standby) | ISB |  | 1 | 2 | μA | VCC=2.5V; VIN=VCC or VSS | 9 |
| Supply Current (standby) | ISB |  | 2 | 5 | μA | VCC=5.0V; VIN=VCC or VSS | 9 |
| Input Leakage Current | IL |  | 0.1 | 3 | μA | VIN=VCC or VSS | 9 |
| Output Leakage Current | IL |  | 0.05 | 3 | μA | VOUT=VCC or VSS | 9 |
| Input Low Level | VIL1 | -0.3 |  |  | V | VCC=1.8V to 5.5V | 9 |
| Output Low Level | VOL3 |  |  | 0.4 | V | VCC=5.0V; IOL=3.0mA | 9 |
| Output Low Level | VOL1 |  |  | 0.2 | V | VCC=1.7V; IOL=0.15mA | 9 |
| Input/Output Capacitance (SDA) | CI/O |  |  | 8 | pF | TA=25℃, f=1.0 MHz, VCC=+1.7V; VIO=0V | 10 |
| Input Capacitance (SCL) | CIN |  |  | 6 | pF | TA=25℃, f=1.0 MHz, VCC=+1.7V; VIN=0V | 10 |
| Clock Frequency, SCL | fSCL |  |  | 400 | KHZ | 1.7V≤VCC﹤2.5V | 10 |
| Clock Frequency, SCL | fSCL |  |  | 1000 | KHZ | 2.5V≤VCC﹤5.5V | 10 |
| Clock Pulse Width Low | tLOW | 1.2 |  |  | μs | 1.7V≤VCC﹤2.5V | 10 |
| Clock Pulse Width Low | tLOW | 0.6 |  |  | μs | 2.5V≤VCC﹤5.5V | 10 |
| Clock Pulse Width High | tHIGH | 0.6 |  |  | μs | 1.7V≤VCC﹤2.5V | 10 |
| Clock Pulse Width High | tHIGH | 0.4 |  |  | μs | 2.5V≤VCC﹤5.5V | 10 |
| Noise Suppression Time | tI |  |  | 50 | ns | 1.7V≤VCC﹤2.5V | 10 |
| Clock Low to Data Out Valid | tAA | 0.1 |  | 0.9 | μs | 1.7V≤VCC﹤2.5V | 10 |
| Clock Low to Data Out Valid | tAA | 0.05 |  | 0.9 | μs | 2.5V≤VCC﹤5.5V | 10 |
| Time the bus must be free before a new transmission can start | tBUF | 1.2 |  |  | μs | 1.7V≤VCC﹤2.5V | 10 |
| Time the bus must be free before a new transmission can start | tBUF | 0.5 |  |  | μs | 2.5V≤VCC﹤5.5V | 10 |
| Start Hold Time | tHD:STA | 0.6 |  |  | μs | 1.7V≤VCC﹤2.5V | 10 |
| Start Hold Time | tHD:STA | 0.25 |  |  | μs | 2.5V≤VCC﹤5.5V | 10 |
| Start Setup Time | tSU:DAT | 0.6 |  |  | μs | 1.7V≤VCC﹤2.5V | 10 |
| Start Setup Time | tSU:DAT | 0.25 |  |  | μs | 2.5V≤VCC﹤5.5V | 10 |
| Data In Hold Time | tHD:DAT | 0 |  |  | μs | 1.7V≤VCC﹤2.5V | 10 |
| Data in Setup Time | tSU:DAT | 100 |  |  | ns | 1.7V≤VCC﹤2.5V | 10 |
| Input Rise Time | tR |  |  | 0.3 | μs | 1.7V≤VCC﹤2.5V | 10 |
| Input Fall Time | tF |  |  | 0.3 | μs | 1.7V≤VCC﹤2.5V | 10 |
| Stop Setup Time | tSu:STO | 0.6 |  |  | μs | 1.7V≤VCC﹤2.5V | 10 |
| Stop Setup Time | tSu:STO | 0.25 |  |  | μs | 2.5V≤VCC﹤5.5V | 10 |
| Data Out Hold Time | tDH | 50 |  |  | ns | 1.7V≤VCC﹤2.5V | 10 |
| Write Cycle Time | twR |  | 3.3 | 5 | ms | 1.7V≤VCC﹤2.5V | 10 |

## CAD (KiCad official)

- Symbol: `AT24C128AN`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files: `at24c128an-etched.step` / `at24c128an-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `at24c128an.step` / `at24c128an.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HGSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603357011379560448) (15 pp, sha256 `ed9771daf6536261`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/at24c128an-datasheet.pdf)