AT17LV010A-10PU

{
  "slug": "at17lv010a-10pu",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech Non-Volatile Memory (ROM), PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "memory",
    "at17lv010a-10pu",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "at17lv010a-10pu.kicad_sym",
    "at17lv010a-10pu.kicad_mod",
    "at17lv010a-10pu.glb",
    "at17lv010a-10pu.step",
    "at17lv010a-10pu.lbr",
    "docs/hero.png",
    "docs/at17lv010a-10pu-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "at17lv010a-10pu-hero.glb",
    "at17lv010a-10pu-hero.overlay.json",
    "at17lv010a-10pu-etched.glb"
  ],
  "component": {
    "mpn": "AT17LV010A-10PU",
    "manufacturer": "Microchip Tech",
    "package": "PDIP-8",
    "pin_count": 8,
    "category": "Memory",
    "subcategory": "Non-Volatile Memory (ROM)",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/59e218d06ad2340bf0c4ccdd7f2dd3ee.pdf",
    "parts": {
      "symbol": "at17lv010a-10pu.kicad_sym",
      "footprint": "at17lv010a-10pu.kicad_mod",
      "model_3d": "at17lv010a-10pu-hero.glb",
      "model_3d_plain": "at17lv010a-10pu-etched.glb",
      "model_3d_step": "at17lv010a-10pu-etched.step",
      "model_3d_step_plain": "at17lv010a-10pu.step",
      "lbr": "at17lv010a-10pu.lbr"
    },
    "distributor_links": {
      "lcsc": "C1519132",
      "digikey": "AT17LV010A-10PU-ND",
      "mouser": "556-AT17LV010A10PU"
    },
    "distributor_check": {
      "checked_at": "2026-10-31T06:21:43Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "AT17LV010A-10PU-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "556-AT17LV010A10PU",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "DATA",
        "type": "bidirectional",
        "description": "Three-state DATA output for configuration, and open-collector bi-directional pin for programming."
      },
      {
        "number": "2",
        "name": "DCLK",
        "type": "bidirectional",
        "description": "Clock output or clock input; rising edges increment the internal address counter and present the next data bit when RESET/OE is High and nCS is Low, otherwise the master drives it Low."
      },
      {
        "number": "3",
        "name": "RESET/OE",
        "type": "input",
        "description": "Reset (active Low) / Output Enable (active High) input: Low resets the address counter, High with nCS Low enables DATA and counting; polarity is programmable and must be programmed active High (RESET active Low) for Altera applications."
      },
      {
        "number": "4",
        "name": "nCS",
        "type": "input",
        "description": "Active-Low chip select: Low (with OE High) lets DCLK increment the address counter and enables DATA; reset with nCS Low makes the device the master in a daisy-chain, reset with nCS High makes it a subsequent device."
      },
      {
        "number": "5",
        "name": "GND",
        "type": "power_in",
        "description": "Ground; a 0.2μF decoupling capacitor between VCC and GND is recommended."
      },
      {
        "number": "6",
        "name": "nCASC",
        "type": "output",
        "description": "Active-Low cascade select output that goes Low when the address counter reaches its maximum value, usually connected to the nCS input of the next device in a daisy-chain."
      },
      {
        "number": "7",
        "name": "SER_EN",
        "type": "input",
        "description": "Serial enable must be held High during FPGA loading (tie to VCC for non-ISP applications); bringing it Low enables the 2-wire serial programming mode."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Power supply pin for 3.3V (±10%) and 5.0V (±10%) operation."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin table lists the 8-lead PDIP column for AT17LV512A/010A with pin 6 as nCASC. The A2 and nCASC; WP1 and READY exist only on the 20-lead PLCC. They are not on the 8-lead PDIP, so I left them out."
        ],
        "pages_sent": 16,
        "cost_usd": 0.1307,
        "at": "2026-10-31T06:21:08"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/59e218d06ad2340bf0c4ccdd7f2dd3ee.pdf",
        "pages": 16,
        "sha256": "c23627784bc00bef",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "at17lv010a-10pu.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          7.874,
          9.27,
          6.98
        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "4a377a56a8d9e9c0b86c095ef9ecc1869ac19e7f5069a3247b294250bf4f235d",
        "checked": "2026-10-31",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "at17lv010a-10pu-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          7.874,
          9.27,
          6.98
        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "4b6cf6aa8817340afb7b37caf34246439758ac1f69c9d0a071b801ab5f5a0542",
        "checked": "2026-10-31",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "8P3",
      "source_page": 13,
      "D": {
        "nom_mm": 9.271,
        "range_mm": [
          9.017,
          10.16
        ]
      },
      "E1": {
        "nom_mm": 6.35,
        "range_mm": [
          6.096,
          7.112
        ]
      },
      "E": {
        "nom_mm": 7.874,
        "range_mm": [
          7.62,
          8.255
        ]
      },
      "e": {
        "nom_mm": 2.54,
        "range_mm": [
          null,
          null
        ]
      },
      "A": {
        "nom_mm": 5.334,
        "range_mm": [
          null,
          5.334
        ]
      },
      "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
      "model_check": {
        "file": "at17lv010a-10pu.step",
        "verdict": "PASS",
        "reasons": [
          "height and body within the datasheet's package drawing"
        ],
        "by": "factory/package_fit.py"
      }
    }
  }
}