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AT17LV010A-10PU
Public Made by Adomby adom
Microchip Tech Non-Volatile Memory (ROM), PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAT17LV010A-10PU
Microchip Tech · Non-Volatile Memory (ROM) · PDIP-8
AT17LV010A-10PU from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DATA | bidirectional | Three-state DATA output for configuration, and open-collector bi-directional pin for programming. |
| 2 | DCLK | bidirectional | Clock output or clock input; rising edges increment the internal address counter and present the next data bit when RESET/OE is High and nCS is Low, otherwise the master drives it Low. |
| 3 | RESET/OE | input | Reset (active Low) / Output Enable (active High) input: Low resets the address counter, High with nCS Low enables DATA and counting; polarity is programmable and must be programmed active High (RESET active Low) for Altera applications. |
| 4 | nCS | input | Active-Low chip select: Low (with OE High) lets DCLK increment the address counter and enables DATA; reset with nCS Low makes the device the master in a daisy-chain, reset with nCS High makes it a subsequent device. |
| 5 | GND | power_in | Ground; a 0.2μF decoupling capacitor between VCC and GND is recommended. |
| 6 | nCASC | output | Active-Low cascade select output that goes Low when the address counter reaches its maximum value, usually connected to the nCS input of the next device in a daisy-chain. |
| 7 | SER_EN | input | Serial enable must be held High during FPGA loading (tie to VCC for non-ISP applications); bringing it Low enables the 2-wire serial programming mode. |
| 8 | VCC | power_in | Power supply pin for 3.3V (±10%) and 5.0V (±10%) operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | PDIP-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature | -40 | 85 | °C | 7 | |||
| Storage Temperature | -65 | 150 | °C | 7 | |||
| Voltage on Any Pin with Respect to Ground | -0.1 | 0.5 | V | max is VCC + 0.5V | 7 | ||
| Supply Voltage | VCC | -0.5 | 7 | V | 7 | ||
| ESD | 2000 | V | RZAP = 1.5K, CZAP = 100 pF | 7 | |||
| Industrial Supply Voltage (3.3V) | VCC | 3 | 3.6 | V | -40C to +85C | 7 | |
| Industrial Supply Voltage (5.0V) | VCC | 4.5 | 5.5 | V | -40C to +85C | 7 | |
| Thermal Resistance Junction to Case, 8P3 PDIP | θJC | 37 | °C/W | 11 | |||
| Thermal Resistance Junction to Ambient, 8P3 PDIP | θJA | 107 | °C/W | Airflow = 0ft/min | 11 | ||
| High-level Input Voltage (3.3V) | VIH | 2 | V | VCC = 3.3V ± 10%; max is VCC | 7 | ||
| Low-level Input Voltage (3.3V) | VIL | 0 | 0.8 | V | VCC = 3.3V ± 10% | 7 | |
| High-level Output Voltage (3.3V) | VOH | 2.4 | V | IOH = -2mA; VCC = 3.3V ± 10% | 7 | ||
| Low-level Output Voltage (3.3V) | VOL | 0.4 | V | IOL = +3mA; VCC = 3.3V ± 10% | 7 | ||
| Supply Current, Active Mode (3.3V) | ICCA | 5 | mA | VCC = 3.3V ± 10% | 7 | ||
| Input or Output Leakage Current (3.3V) | IL | -10 | 10 | μA | VIN = VCC or GND; VCC = 3.3V ± 10% | 7 | |
| Supply Current, Standby Mode (3.3V) | ICCS | 100 | μA | VCC = 3.3V ± 10% | 7 | ||
| High-level Input Voltage (5.0V) | VIH | 2 | V | VCC = 5.0V ± 10%; max is VCC | 8 | ||
| Low-level Input Voltage (5.0V) | VIL | 0 | 0.8 | V | VCC = 5.0V ± 10% | 8 | |
| High-level Output Voltage (5.0V) | VOH | 3.76 | V | IOH = -2mA; VCC = 5.0V ± 10% | 8 | ||
| Low-level Output Voltage (5.0V) | VOL | 0.37 | V | IOL = +3mA; VCC = 5.0V ± 10% | 8 | ||
| Supply Current, Active Mode (5.0V) | ICCA | 10 | mA | VCC = 5.0V ± 10% | 8 | ||
| Input or Output Leakage Current (5.0V) | IL | -10 | 10 | μA | VIN = VCC or GND; VCC = 5.0V ± 10% | 8 | |
| Supply Current, Standby Mode (5.0V) | ICCS1 | 200 | μA | VCC = 5.0V ± 10% | 8 | ||
| OE to Data Delay (3.3V) | TOE | 55 | ns | VCC = 3.3V ± 10%; AC test load = 50pF | 8 | ||
| CE to Data Delay (3.3V) | TCE | 60 | ns | VCC = 3.3V ± 10%; AC test load = 50pF | 8 | ||
| CLK to Data Delay (3.3V) | TCAC | 60 | ns | VCC = 3.3V ± 10%; AC test load = 50pF | 8 | ||
| Data Hold from CE, OE, or CLK (3.3V) | TOH | 0 | ns | VCC = 3.3V ± 10% | 8 | ||
| CE or OE to Data Float Delay (3.3V) | TDF | 50 | ns | VCC = 3.3V ± 10%; float delays measured with 5pF AC loads | 8 | ||
| CLK Low Time (3.3V) | TLC | 25 | ns | VCC = 3.3V ± 10% | 8 | ||
| CLK High Time (3.3V) | THC | 25 | ns | VCC = 3.3V ± 10% | 8 | ||
| CE Setup Time to CLK (3.3V) | TSCE | 35 | ns | to guarantee proper counting; VCC = 3.3V ± 10% | 8 | ||
| CE Hold Time from CLK (3.3V) | THCE | 0 | ns | to guarantee proper counting; VCC = 3.3V ± 10% | 8 | ||
| OE High Time (3.3V) | THOE | 25 | ns | guarantees counter is reset; VCC = 3.3V ± 10% | 8 | ||
| Maximum Input Clock Frequency (3.3V) | FMAX | 10 | MHz | VCC = 3.3V ± 10% | 8 | ||
| CLK to Data Float Delay, Cascading (3.3V) | TCDF | 50 | ns | VCC = 3.3V ± 10%; float delays measured with 5pF AC loads | 9 | ||
| CLK to CEO Delay, Cascading (3.3V) | TOCK | 55 | ns | VCC = 3.3V ± 10%; AC test load = 50pF | 9 | ||
| CE to CEO Delay, Cascading (3.3V) | TOCE | 40 | ns | VCC = 3.3V ± 10%; AC test load = 50pF | 9 | ||
| RESET/OE to CEO Delay, Cascading (3.3V) | TOOE | 35 | ns | VCC = 3.3V ± 10%; AC test load = 50pF | 9 | ||
| Maximum Input Clock Frequency, Cascading (3.3V) | FMAX | 10 | MHz | VCC = 3.3V ± 10% | 9 | ||
| OE to Data Delay (5.0V) | TOE | 35 | ns | VCC = 5.0V ± 10%; AC test load = 50pF | 9 | ||
| CE to Data Delay (5.0V) | TCE | 45 | ns | VCC = 5.0V ± 10%; AC test load = 50pF | 9 | ||
| CLK to Data Delay (5.0V) | TCAC | 50 | ns | VCC = 5.0V ± 10%; AC test load = 50pF | 9 | ||
| Data Hold from CE, OE, or CLK (5.0V) | TOH | 0 | ns | VCC = 5.0V ± 10% | 9 | ||
| CE or OE to Data Float Delay (5.0V) | TDF | 50 | ns | VCC = 5.0V ± 10%; float delays measured with 5pF AC loads | 9 | ||
| CLK Low Time (5.0V) | TLC | 20 | ns | VCC = 5.0V ± 10% | 9 | ||
| CLK High Time (5.0V) | THC | 20 | ns | VCC = 5.0V ± 10% | 9 | ||
| CE Setup Time to CLK (5.0V) | TSCE | 25 | ns | to guarantee proper counting; VCC = 5.0V ± 10% | 9 | ||
| CE Hold Time from CLK (5.0V) | THCE | 0 | ns | to guarantee proper counting; VCC = 5.0V ± 10% | 9 | ||
| OE High Time (5.0V) | THOE | 20 | ns | guarantees counter is reset; VCC = 5.0V ± 10% | 9 | ||
| Maximum Input Clock Frequency (5.0V) | FMAX | 15 | MHz | VCC = 5.0V ± 10% | 9 | ||
| CLK to Data Float Delay, Cascading (5.0V) | TCDF | 50 | ns | VCC = 5.0V ± 10%; float delays measured with 5pF AC loads | 10 | ||
| CLK to CEO Delay, Cascading (5.0V) | TOCK | 40 | ns | VCC = 5.0V ± 10%; AC test load = 50pF | 10 | ||
| CE to CEO Delay, Cascading (5.0V) | TOCE | 35 | ns | VCC = 5.0V ± 10%; AC test load = 50pF | 10 | ||
| RESET/OE to CEO Delay, Cascading (5.0V) | TOOE | 30 | ns | VCC = 5.0V ± 10%; AC test load = 50pF | 10 | ||
| Maximum Input Clock Frequency, Cascading (5.0V) | FMAX | 12.5 | MHz | VCC = 5.0V ± 10% | 10 |
CAD (KiCad official)
- Symbol:
AT17LV010A-10PU - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files:
at17lv010a-10pu-etched.step/at17lv010a-10pu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at17lv010a-10pu.step/at17lv010a-10pu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (16 pp, sha256
c23627784bc00bef, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).