APS6404L-3SQR-SN

{
  "schema_version": 1,
  "type": "component",
  "slug": "aps6404l-3sqr-sn",
  "title": "APS6404L-3SQR-SN",
  "brief": "AP MEMORY Global Sourcing Parts, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "global sourcing parts",
    "aps6404l-3sqr-sn",
    "factory-2.0.0",
    "extractor-text"
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  "component": {
    "mpn": "APS6404L-3SQR-SN",
    "manufacturer": "AP MEMORY",
    "package": "SOP-8",
    "pin_count": 8,
    "category": "Global Sourcing Parts",
    "subcategory": "Global Sourcing Parts",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/e8190d37d866392254d3573489478495.pdf",
    "parts": {
      "symbol": "aps6404l-3sqr-sn.kicad_sym",
      "footprint": "aps6404l-3sqr-sn.kicad_mod",
      "model_3d": "aps6404l-3sqr-sn-hero.glb",
      "model_3d_plain": "aps6404l-3sqr-sn-etched.glb",
      "model_3d_step": "aps6404l-3sqr-sn-etched.step",
      "model_3d_step_plain": "aps6404l-3sqr-sn.step",
      "lbr": "aps6404l-3sqr-sn.lbr"
    },
    "distributor_links": {
      "lcsc": "C5333729"
    },
    "distributor_check": {
      "checked_at": "2026-10-22T21:53:21Z",
      "source": "Component Ocean /api/assign-pns",
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        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
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    },
    "pins": [
      {
        "number": "1",
        "name": "CE#",
        "type": "input",
        "description": "Chip select, active low; when CE#=1 the chip is in standby state, and it must be raised high to terminate every read or write command."
      },
      {
        "number": "2",
        "name": "SO/SIO[1]",
        "type": "bidirectional",
        "description": "Serial output in SPI mode and IO[1] in SPI Quad and QPI modes."
      },
      {
        "number": "3",
        "name": "SIO[2]",
        "type": "bidirectional",
        "description": "Not used in SPI mode; IO[2] in SPI Quad and QPI modes."
      },
      {
        "number": "4",
        "name": "VSS",
        "type": "power_in",
        "description": "Core supply ground."
      },
      {
        "number": "5",
        "name": "SI/SIO[0]",
        "type": "bidirectional",
        "description": "Serial input in SPI mode and IO[0] in SPI Quad and QPI modes."
      },
      {
        "number": "6",
        "name": "SCLK",
        "type": "input",
        "description": "Clock signal that latches all instructions, addresses and data; must remain low during power-up initialization, with max clock rate 133MHz at VDD=3.0V+/-10%."
      },
      {
        "number": "7",
        "name": "SIO[3]",
        "type": "bidirectional",
        "description": "Not used in SPI mode; IO[3] in SPI Quad and QPI modes."
      },
      {
        "number": "8",
        "name": "VDD",
        "type": "power_in",
        "description": "Core supply, 2.7V to 3.6V (absolute maximum -0.4 to +4.0V), with a 1µF low-ESR ceramic decoupling capacitor recommended close to the pin."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin 6 is labeled SCLK in the package diagram (page 4) but CLK in the signal table (page 8); same fun; Pin types for the SIO pins are inferred from the signal table 'IO' type; the datasheet does not use ",
          "1/8 pins cited to the wrong page (name found elsewhere): ['6:SCLK@p8']"
        ],
        "pages_sent": 24,
        "cost_usd": 0.1278,
        "at": "2026-10-22T21:53:11"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/e8190d37d866392254d3573489478495.pdf",
        "pages": 24,
        "sha256": "3ab2622938f523db",
        "source_tier": "lcsc"
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      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
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      "Package": "SOP-8",
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      "Pins": "8"
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        "page": 4,
        "doc": "ds.pdf",
        "plating": "tin"
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          "max": 3.6,
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        {
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          "unit": "V",
          "min": -0.4,
          "typ": null,
          "max": 0.2,
          "conditions": "printed VDD-0.4 min, VDD+0.2 max (relative to VDD)",
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          "name": "Read/Write current",
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          "source_page": 22,
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        {
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          "max": 250,
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          "name": "Standby current (standard room temp)",
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          "name": "Voltage to any ball except VDD relative to VSS",
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        {
          "name": "Storage Temperature",
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        {
          "name": "Operating Temperature (standard)",
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          "conditions": "VOUT=0V",
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          "name": "Load Capacitance",
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        {
          "name": "CLK period - SPI Read (h03)",
          "symbol": "tCLK",
          "kind": "timing",
          "unit": "ns",
          "min": 30.3,
          "typ": null,
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          "conditions": "33MHz",
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          "name": "CLK period - QPI Read (h0B)",
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        {
          "name": "CLK period - all other operations PKG 3.3V",
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          "kind": "timing",
          "unit": "ns",
          "min": 9.17,
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          "name": "CLK period - all other operations",
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          "kind": "timing",
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          "min": 11.9,
          "typ": null,
          "max": null,
          "conditions": "84MHz",
          "source_page": 23,
          "source": "datasheet"
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        {
          "name": "Clock high/low width",
          "symbol": "tCH/tCL",
          "kind": "timing",
          "unit": "tCLK(min)",
          "min": 0.45,
          "typ": null,
          "max": 0.55,
          "conditions": "",
          "source_page": 23,
          "source": "datasheet"
        },
        {
          "name": "CLK rise or fall time",
          "symbol": "tKHKL",
          "kind": "timing",
          "unit": "ns",
          "min": null,
          "typ": null,
          "max": 1.5,
          "conditions": "Measured from 20% to 80% of VDD",
          "source_page": 23,
          "source": "datasheet"
        },
        {
          "name": "CE# HIGH between subsequent burst operations",
          "symbol": "tCPH",
          "kind": "timing",
          "unit": "ns",
          "min": 18,
          "typ": null,
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          "source": "datasheet"
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        {
          "name": "CE# low pulse width",
          "symbol": "tCEM",
          "kind": "timing",
          "unit": "µs",
          "min": null,
          "typ": null,
          "max": 8,
          "conditions": "Standard grade",
          "source_page": 23,
          "source": "datasheet"
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        {
          "name": "CE# setup time to CLK rising edge",
          "symbol": "tCSP",
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          "min": 2.5,
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        {
          "name": "CE# hold time from CLK rising edge",
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          "min": 3,
          "typ": null,
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        {
          "name": "Setup time to active CLK edge",
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          "min": 2,
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        {
          "name": "Hold time from active CLK edge",
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          "min": 2,
          "typ": null,
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          "conditions": "",
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          "source": "datasheet"
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        {
          "name": "Chip disable to DQ output high-Z",
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          "source_page": 23,
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        {
          "name": "CLK to output delay",
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          "min": 2,
          "typ": null,
          "max": 5.5,
          "conditions": "",
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        {
          "name": "Data hold time from clock falling edge",
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          "kind": "timing",
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          "min": 1.5,
          "typ": null,
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        {
          "name": "Time between end of RST CMD to next valid CMD",
          "symbol": "tRST",
          "kind": "timing",
          "unit": "ns",
          "min": 50,
          "typ": null,
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          "source": "datasheet"
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