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APS6404L-3SQR-SN
Public Made by Adomby adom
AP MEMORY Global Sourcing Parts, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAPS6404L-3SQR-SN
AP MEMORY · Global Sourcing Parts · SOP-8
APS6404L-3SQR-SN from AP MEMORY, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CE# | input | Chip select, active low; when CE#=1 the chip is in standby state, and it must be raised high to terminate every read or write command. |
| 2 | SO/SIO[1] | bidirectional | Serial output in SPI mode and IO[1] in SPI Quad and QPI modes. |
| 3 | SIO[2] | bidirectional | Not used in SPI mode; IO[2] in SPI Quad and QPI modes. |
| 4 | VSS | power_in | Core supply ground. |
| 5 | SI/SIO[0] | bidirectional | Serial input in SPI mode and IO[0] in SPI Quad and QPI modes. |
| 6 | SCLK | input | Clock signal that latches all instructions, addresses and data; must remain low during power-up initialization, with max clock rate 133MHz at VDD=3.0V+/-10%. |
| 7 | SIO[3] | bidirectional | Not used in SPI mode; IO[3] in SPI Quad and QPI modes. |
| 8 | VDD | power_in | Core supply, 2.7V to 3.6V (absolute maximum -0.4 to +4.0V), with a 1µF low-ESR ceramic decoupling capacitor recommended close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | AP MEMORY |
| Package | SOP-8 |
| Category | Global Sourcing Parts |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 2.7 | 3.6 | V | 22 | ||
| Input high voltage | VIH | -0.4 | 0.2 | V | printed VDD-0.4 min, VDD+0.2 max (relative to VDD) | 22 | |
| Input low voltage | VIL | -0.2 | 0.4 | V | 22 | ||
| Output high voltage | VOH | 0.8 | V | IOH=-0.2mA; printed 0.8 VDD | 22 | ||
| Output low voltage | VOL | 0.2 | V | IOL=+0.2mA; printed 0.2 VDD | 22 | ||
| Input leakage current | ILI | 1 | µA | 22 | |||
| Output leakage current | ILO | 1 | µA | 22 | |||
| Read/Write current | ICC | 5.5 | 7 | mA | Output load current not included; typical 5.5mA at 133MHz | 22 | |
| Standby current (standard temp) | ISBSTD | 250 | µA | CLK in DC low state | 22 | ||
| Standby current (standard room temp) | ISBSTDroom | 100 | 140 | µA | CLK in DC low state | 22 | |
| Voltage to any ball except VDD relative to VSS | VT | -0.4 | V | printed -0.4 to VDD+0.4 | 20 | ||
| Voltage on VDD supply relative to VSS | VDD | -0.4 | 4 | V | 20 | ||
| Storage Temperature | TSTG | -55 | 150 | °C | 20 | ||
| Operating Temperature (standard) | -40 | 85 | °C | 21 | |||
| Input Pin Capacitance | CIN | 6 | pF | VIN=0V | 20 | ||
| Output Pin Capacitance | COUT | 8 | pF | VOUT=0V | 20 | ||
| Load Capacitance | CL | 15 | pF | 20 | |||
| CLK period - SPI Read (h03) | tCLK | 30.3 | ns | 33MHz | 23 | ||
| CLK period - QPI Read (h0B) | tCLK | 15.1 | ns | 66MHz | 23 | ||
| CLK period - all other operations PKG 3V | tCLK | 7.5 | ns | 133MHz | 23 | ||
| CLK period - all other operations PKG 3.3V | tCLK | 9.17 | ns | 109MHz | 23 | ||
| CLK period - all other operations | tCLK | 11.9 | ns | 84MHz | 23 | ||
| Clock high/low width | tCH/tCL | 0.45 | 0.55 | tCLK(min) | 23 | ||
| CLK rise or fall time | tKHKL | 1.5 | ns | Measured from 20% to 80% of VDD | 23 | ||
| CE# HIGH between subsequent burst operations | tCPH | 18 | ns | 23 | |||
| CE# low pulse width | tCEM | 8 | µs | Standard grade | 23 | ||
| CE# setup time to CLK rising edge | tCSP | 2.5 | ns | 23 | |||
| CE# hold time from CLK rising edge | tCHD | 3 | ns | 23 | |||
| Setup time to active CLK edge | tSP | 2 | ns | 23 | |||
| Hold time from active CLK edge | tHD | 2 | ns | 23 | |||
| Chip disable to DQ output high-Z | tHZ | 5.5 | ns | 23 | |||
| CLK to output delay | tACLK | 2 | 5.5 | ns | 23 | ||
| Data hold time from clock falling edge | tKOH | 1.5 | ns | 23 | |||
| Time between end of RST CMD to next valid CMD | tRST | 50 | ns | 23 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | package including 8-lead USON-8L 3x2mm. 3.1 Package Types : SOP / USON (SN, ZR) , not to scale, Top view | 4 |
CAD (KiCad official)
- Symbol:
APS6404L-3SQR-SN - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
aps6404l-3sqr-sn-etched.step/aps6404l-3sqr-sn-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aps6404l-3sqr-sn.step/aps6404l-3sqr-sn.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: AP MEMORY datasheet (24 pp, sha256
3ab2622938f523db, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).