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AP7362-33SP-13

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Diodes Incorporated Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SO-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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docs ap7362-33sp-13: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 2mo ago
ap7362-33sp-13-etched.fit.json ap7362-33sp-13: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ap7362-33sp-13-etched.glb ap7362-33sp-13: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ap7362-33sp-13-etched.step ap7362-33sp-13: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ap7362-33sp-13.glb Publish 0.1.0 · Ray 2mo ago
ap7362-33sp-13.kicad_mod footprint + symbol: give this part its thermal pad. It shipped SOIC-8_3.9x4.9mm_P1.27mm, which has no exposed pad at al… · Ray 2mo ago
ap7362-33sp-13.kicad_sym footprint + symbol: give this part its thermal pad. It shipped SOIC-8_3.9x4.9mm_P1.27mm, which has no exposed pad at al… · Ray 2mo ago
ap7362-33sp-13.lbr footprint + symbol: give this part its thermal pad. It shipped SOIC-8_3.9x4.9mm_P1.27mm, which has no exposed pad at al… · Ray 2mo ago
ap7362-33sp-13.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.2.0 · Ray 2mo ago
pads.json footprint + symbol: give this part its thermal pad. It shipped SOIC-8_3.9x4.9mm_P1.27mm, which has no exposed pad at al… · Ray 2mo ago
page.json ap7362-33sp-13: specified limits as data (metadata.characteristics, 22 rows from the datasheet) · Ray 19d ago
README.md ap7362-33sp-13: specified limits as data (metadata.characteristics, 22 rows from the datasheet) · Ray 19d ago

AP7362-33SP-13

Diodes Incorporated · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SO-8-EP

AP7362-33SP-13 from Diodes Incorporated, in a SO-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Device ground return. Also serves as the reference for the internal band-gap and output feedback network. Should be tied to the exposed pad copper plane.
2 EN input Enable input, active high. VIH ≥ 1.4V turns the regulator on; VIL ≤ 0.65V places the device in shutdown (IGND ≈ 25nA). Absolute-max range -0.3V to 6.0V; do not float.
3 IN power_in Voltage input pin. Operating range 2.2V to 5.5V (absolute-max 6.0V). Pins 3 and 4 are internally connected and must be tied together on the PCB; place a ≥10µF input capacitor close to these pins.
4 IN power_in Voltage input pin. Internally strapped to pin 3; tie both externally and decouple with a ≥10µF ceramic input capacitor.
5 OUT power_out Regulated 3.3V output pin (fixed AP7362-33 variant). Rated 1.5A continuous. Pins 5, 6, 7 are internally connected and must be tied together; requires a ≥10µF output capacitor (any type) for stability.
6 OUT power_out Regulated output pin, internally strapped to pins 5 and 7. Tie all three externally to share the 1.5A load current and reduce metal resistance.
7 OUT power_out Regulated output pin, internally strapped to pins 5 and 6. Tie all three externally at the ≥10µF output capacitor.
8 NC unconnected No internal connection on this fixed-output (AP7362-33) variant. On the adjustable AP7362 variant this pin is the ADJ feedback input; leave it open or tie to ground for the fixed version.
EP EP power_in Exposed thermal pad on the package underside. Die is electrically connected to EP; must be soldered to a copper area for heat removal (θJA ≈ 52.8 °C/W). Connect externally to GND, but do not use as the only ground connection.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SO-8-EP
Category PMIC
Pins 9

Ordering variants

  • AP7362-33SP-13
  • AP7362-33SP-13HA-7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage tolerance (blank suffix, ±3.5%) VADJ Tolerance -3.5 3.5 % Ordering info: VADJ Tolerance BLANK = ±3.5%; applies to AP7362-33SP-13 (no A suffix) 11
Ground Pin Current in Normal Operation Mode IGND 1 1.2 mA IOUT = 10mA to 1.5A, TA = +25°C 3
Ground Pin Current in Normal Operation Mode (over temp) IGND 1.3 mA IOUT = 10mA to 1.5A, over temp 3
Ground Pin Current VEN < VIL ISHDN 0.025 0.125 μA VEN < VIL, TA = +25°C 3
Ground Pin Current VEN < VIL (over temp) ISHDN 15 μA VEN < VIL, over temp 3
Dropout Voltage VDROPOUT 190 240 mV IOUT = 1.5A, VOUT = 2.5V, TA = +25°C 3
Dropout Voltage (over temp) VDROPOUT 280 mV IOUT = 1.5A, VOUT = 2.5V, over temp 3
Short Circuit Current (over temp) ISC 2 A OUT grounded, over temp 3
Enable Logic High VIH 1.4 V VIN = VIN-MIN to VIN-MAX, over temp 3
Enable Logic Low VIL 0.65 V VIN = VIN-MIN to VIN-MAX, over temp 3
Input Voltage VIN 2.2 5.5 V 3
Output Current IOUT 0 1.5 A 3
Operating Ambient Temperature TA -40 85 C 3
Operating Junction Temperature TJ -40 125 C Note 5: must be evaluated and derated based on TA, PD, TJ-MAX and θJA 3
Input Voltage VIN -0.3 6 V 2
OUT, EN Voltage VOUT, VEN -0.3 6 V 2
ESD HBM Human Body Model ESD Protection ESD HBM 2000 V Human Body Model 2
ESD MM Machine Model ESD Protection ESD MM 200 V Machine Model 2
Storage Temperature Range TST -65 150 °C 2
Maximum Junction Temperature TJ 150 °C 2
Thermal Resistance Junction-to-Ambient, SO-8EP θJA 52.8 °C/W Device mounted on 2in x 2in FR-4 substrate PCB, 2oz copper, minimum recommended pad layout (Note 8) 4
Thermal Resistance Junction-to-Case, SO-8EP θJC 10 °C/W Note 8 4

CAD (KiCad official)

  • Symbol: AP7362-33SP-13
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8-EP (KiCad packages3D, STEP)
  • 3D model files: ap7362-33sp-13-etched.step / ap7362-33sp-13-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ap7362-33sp-13.step / ap7362-33sp-13.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ap7362-33sp-13.step 122 KB You want the bare part, or you mark your own boards.
ap7362-33sp-13-etched.step 2.9 MB You want the part with AP7362-33SP-13 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 695 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (15 pp, sha256 9b2fca67bed660a2, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF