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AP7173-FNG-7

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Diodes Incorporated Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TDFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AP7173-FNG-7

Diodes Incorporated · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TDFN-10-EP(3x3)

AP7173-FNG-7 from Diodes Incorporated, in a TDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Power input pin for the regulator; the datasheet's recommended VIN range is 1.0V to 5.5V.
2 IN power_in Power input pin for the regulator; the datasheet's recommended VIN range is 1.0V to 5.5V.
3 PG output Open-drain power-good output that is pulled low when VOUT is below the PG threshold and goes high-impedance when VOUT exceeds it; use a 10kΩ to 1MΩ pull-up to a supply of up to 5.5V.
4 VCC power_in Bias input that supplies the internal control circuitry and should be kept higher than VIN.
5 EN input Enable pin that must be driven high or low and must not be left floating; high enables the regulator and low puts it into shutdown.
6 GND power_in Ground reference pin for the regulator.
7 SS passive Soft-start pin; a capacitor from this pin to ground sets the output soft-start ramp time, and the time is typically 100µS if no capacitor is connected.
8 FB input Feedback pin that connects to an external voltage divider to set the output voltage.
9 OUT power_out Regulated output pin of the LDO.
10 OUT power_out Regulated output pin of the LDO.
11 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package TDFN-10-EP(3x3)
Category Power Management (PMIC)
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage (VIN) VIN 1 5.5 V Note 6: at VIN=1V, maximum load currents may be lower than 1.5A 4
Bias Voltage VVCC 2.7 5.5 V 4
Output Current IOUT 0 1.5 A 4
Operating Ambient Temperature TA -40 85 ºC 4
ESD Protection, Human Body Model ESD HBM 4000 V Human Body Model ESD Protection 4
ESD Protection, Machine Model ESD MM 350 V Machine Model ESD Protection 4
Input Voltage Range (VIN, VVCC) VIN, VVCC -0.3 6 V 4
Enable Voltage Range VEN -0.3 6 V 4
Power-Good Voltage Range VPG -0.3 6 V 4
Soft-Start Voltage Range VSS -0.3 6 V 4
Feedback Voltage Range VFB -0.3 6 V 4
Output Voltage Range VOUT -0.3 V Upper limit printed as VIN +0.3 V 4
Continuous Total Power Dissipation (DFN3030-10) PD 3690 mW DFN3030-10; ratings apply to ambient temperature at 25°C (Note 5) 4
Junction Temperature Range TJ -40 150 ºC 4
Storage Junction Temperature Range TST -65 150 ºC 4
Input Voltage Range VIN 5.5 V 5
Bias Pin Voltage Range VVCC 2.7 5.5 V Note 7: VVCC should be higher or equal to VIN 5
Internal Reference (Adj.) VREF 0.792 0.8 0.808 V TA = +25 ºC 5
Output Voltage Range VOUT 0.8 3.3 V VIN= 5V, IOUT= 1.5A 5
Accuracy (Note 8) -2 0.5 2 % 2.97V≤VVCC≤5.5V, 50mA≤IOUT≤1.5A 5
Dropout Voltage (Note 9) VDO 165 270 mV IOUT = 1.5A, VVCC-VOUT(NOM)≥3.25V 5
Dropout Voltage (VIN = VVCC) VDO 1.5 1.7 V IOUT= 1.5A, VIN = VVCC 5
Current Limit ICL 2 3 4 A VOUT = 80% x VOUT (NOM) 5
Short-Circuit Current ISHORT 0.6 1 A VOUT < 0.2V 5
Bias Pin Current IVCC 1 2 mA 5
Shutdown Supply Current (IGND) ISHDN 1 50 µA VEN≤0.4V 5
Feedback Pin Current IFB -1 0.1 1 µA 5
Enable Input High Level VEN, HI 1.1 5.5 V 5
Enable Input Low Level VEN, LO 0 0.4 V 5
PG Trip Threshold VPG, TH 85 90 94 %VOUT VOUT decreasing 5
Line Regulation ΔVOUT /ΔVIN / VOUT 0.03 %/V VOUT (NOM) + 0.5≤VIN, 5.5V 5
Load Regulation ΔVOUT /VOUT /ΔIOUT 0.09 %/A 50mA≤IOUT≤1.5A 5
Junction Temperature Specified Limit (application note) TJ 125 ºC Application note: limit to which device junction temperature must be held 11
Enable Pin Current IEN 0.1 1 µA VEN= 5V 5
PG Output Low Voltage VPG, LO 0.3 V IPG= 1mA (sinking), VOUT<VPG, TH 5
PG Leakage Current IPG, LKG 0.1 1 µA VPG= 5.25V, VOUT>VPG, TH 5
Power-Supply Rejection (VIN to VOUT), 1 kHz PSRR 60 dB 1KHz, IOUT= 1A, VIN= 1.8V, VOUT= 1.5V 5
Power-Supply Rejection (VIN to VOUT), 300 kHz PSRR 30 dB 300KHz, IOUT =1A, VIN= 1.8V, VOUT =1.5V 5
Power-Supply Rejection (VVCC to VOUT), 1 kHz PSRR 50 dB 1KHz, IOUT = 1A, VIN= 1.8V, VOUT =1.5V 5
Power-Supply Rejection (VVCC to VOUT), 300 kHz PSRR 30 dB 300KHz, IOUT = 1A, VIN= 1.8V, VOUT =1.5V 5
Startup Time TST 100 µS RLOAD for IOUT = 1.0A, CSS = open 5
Soft-Start Charging Current ISS 440 nA VSS= 0.4V 5
Enable Pin Hysteresis VEN, HYS 50 mV 5
PG Trip Hysteresis VPG, HYS 3 %VOUT 5
Thermal Shutdown Temperature (shutdown) TSD 150 ºC Shutdown, temperature increasing 5
Thermal Shutdown Temperature (reset) TSD 130 ºC Reset, temperature decreasing 5
Thermal Resistance Junction-to-Ambient (DFN3030-10) θJA 35 oC/W DFN3030-10 (Note 10): FR-4 2s2p, 2"x2" PCB, 2oz copper, large pad pattern 5
Thermal Resistance Junction-to-Case (DFN3030-10) θJC 4.9 oC/W DFN3030-10 (Note 10): FR-4 2s2p, 2"x2" PCB, 2oz copper, large pad pattern 5

CAD (KiCad official)

  • Symbol: AP7173-FNG-7
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: TDFN-10-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: ap7173-fng-7-etched.step / ap7173-fng-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ap7173-fng-7.step / ap7173-fng-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (15 pp, sha256 35704e6ac6d2f4f6, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF