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AK5578EN

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Asahi Kasei Microdevices Digital To Analog Converters (DACs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AK5578EN

Asahi Kasei Microdevices · Digital To Analog Converters (DACs) · VQFN-64-EP(9x9)

AK5578EN from Asahi Kasei Microdevices, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVSS1 power_in Analog ground for the AIN1-4 channels.
2 AVDD1 power_in Analog power supply for the AIN1-4 channels, 4.75-5.25 V (5.0 V typ).
3 AIN3P input Channel 3 positive differential analog input.
4 AIN3N input Channel 3 negative differential analog input.
5 VREFL2 input ADC low-level voltage reference input for channels 3-4, normally connected to AVSS.
6 VREFH2 input ADC high-level voltage reference input for channels 3-4; must not exceed AVDD+0.1 V.
7 AIN4N input Channel 4 negative differential analog input.
8 AIN4P input Channel 4 positive differential analog input.
9 AIN5P input Channel 5 positive differential analog input.
10 AIN5N input Channel 5 negative differential analog input.
11 VREFH3 input ADC high-level voltage reference input for channels 5-6; must not exceed AVDD+0.1 V.
12 VREFL3 input ADC low-level voltage reference input for channels 5-6, normally connected to AVSS.
13 AIN6N input Channel 6 negative differential analog input.
14 AIN6P input Channel 6 positive differential analog input.
15 AVDD2 power_in Analog power supply for the AIN5-8 channels, 4.75-5.25 V (5.0 V typ).
16 AVSS2 power_in Analog ground for the AIN5-8 channels.
17 AIN7P input Channel 7 positive differential analog input.
18 AIN7N input Channel 7 negative differential analog input.
19 VREFH4 input ADC high-level voltage reference input for channels 7-8; must not exceed AVDD+0.1 V.
20 VREFL4 input ADC low-level voltage reference input for channels 7-8, normally connected to AVSS.
21 AIN8N input Channel 8 negative differential analog input.
22 AIN8P input Channel 8 positive differential analog input.
23 TEST input TEST enable pin, internally pulled down by 100 kΩ; connect to DVSS when unused.
24 MCLK input Master clock input pin.
25 TVDD power_in Digital I/O buffer and LDO power supply, 1.7-1.98 V when LDOE is L or 3.0-3.6 V when LDOE is H.
26 DVSS power_in Digital ground pin; must be connected to the same analog ground plane as AVSS1/2.
27 VDD18 power_in Digital core power supply, 1.7-1.98 V when LDOE is L; when LDOE is H it is the LDO stabilization capacitor connection (Hi-Z, pulled down by 500 Ω).
28 PDN input Reset and power-down pin: L resets and powers down the device, H enables normal operation.
29 PW0 input Power management pin and channel summation select pin (bit 0).
30 PW1 input Power management pin and channel summation select pin (bit 1).
31 PW2 input Power management pin and channel summation select pin (bit 2).
32 MSN input Master/slave select: L selects slave mode, H selects master mode.
33 BICK/DCLK bidirectional Audio serial bit clock: input in PCM slave mode and output in PCM master mode; DSD clock output (DCLK) in DSD mode; internally pulled down by 100 kΩ.
34 LRCK/DSDOL1 bidirectional Channel clock: input in PCM slave mode and output in PCM master mode; DSD serial data output for AIN1 in DSD mode; internally pulled down by 100 kΩ.
35 TDMIN/DSDOR1 input TDM data input in PCM mode (internally pulled down by 100 kΩ); DSD serial data output for AIN2 in DSD mode.
36 SDTO1/DSDOL2 output Serial audio data output for AIN1 and AIN2 in PCM mode; DSD serial data output for AIN3 in DSD mode; L in power-down.
37 SDTO2/DSDOR2 output Serial audio data output for AIN3 and AIN4 in PCM mode; DSD serial data output for AIN4 in DSD mode; L in power-down.
38 SDTO3/DSDOL3 output Serial audio data output for AIN5 and AIN6 in PCM mode; DSD serial data output for AIN5 in DSD mode; L in power-down.
39 SDTO4/DSDOR3 output Serial audio data output for AIN7 and AIN8 in PCM mode; DSD serial data output for AIN6 in DSD mode; L in power-down.
40 DSDOL4 output DSD serial data output for AIN7; L in power-down.
41 DSDOR4 output DSD serial data output for AIN8; L in power-down.
42 OVF output Analog input overflow flag output; L in power-down.
43 CKS0/SDA/CDTI input Clock mode select pin; serves as SDA (I2C control data I/O, Hi-Z in power-down) or CDTI (3-wire control data input) depending on control mode.
44 CKS1/CAD0_I2C/CSN input Clock mode select pin; serves as chip address 0 in I2C mode or CSN chip select in 3-wire mode.
45 CKS2/SCL/CCLK input Clock mode select pin; serves as SCL (I2C control clock) or CCLK (3-wire control clock) depending on control mode.
46 CKS3/CAD1 input Clock mode select pin; serves as chip address 1 in I2C or 3-wire control mode.
47 SLOW/DCKB input Slow roll-off digital filter select in PCM mode; DCLK polarity select in DSD mode.
48 SD/PMOD input Short delay digital filter select in PCM mode; DSD phase modulation mode select in DSD mode.
49 DIF0/DSDSEL0 input Audio data format select in PCM mode (L: MSB justified, H: I2S); DSD sampling rate control in DSD mode.
50 DIF1/DSDSEL1 input Audio data format select in PCM mode (L: 24-bit, H: 32-bit); DSD sampling rate control in DSD mode.
51 TDM0 input TDM interface format select; must be fixed to L in DSD mode.
52 TDM1 input TDM interface format select; must be fixed to L in DSD mode.
53 PSN/CAD0_SPI input Control mode select when I2C pin is H (L: I2C bus control, H: parallel control); chip address 0 in 3-wire mode when I2C pin is L.
54 I2C input Control mode select: L selects 3-wire serial control, H selects I2C bus or parallel control.
55 DP input DSD mode enable: L selects PCM mode, H selects DSD mode.
56 HPFE/DCKS input High-pass filter enable in PCM mode (L: disable, H: enable); master clock frequency select (DCKS) in DSD mode.
57 LDOE input LDO enable: L disables the internal LDO, H enables it; internally pulled down by 100 kΩ.
58 ODP input Optimal data placement mode select pin.
59 AIN1P input Channel 1 positive differential analog input.
60 AIN1N input Channel 1 negative differential analog input.
61 VREFL1 input ADC low-level voltage reference input for channels 1-2, normally connected to AVSS.
62 VREFH1 input ADC high-level voltage reference input for channels 1-2; must not exceed AVDD+0.1 V.
63 AIN2N input Channel 2 negative differential analog input.
64 AIN2P input Channel 2 positive differential analog input.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Asahi Kasei Microdevices
Package VQFN-64-EP(9x9)
Category ADC/DAC/Data Conversion
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog (AVDD pin) absolute maximum AVDDam -0.3 6 V VSS=0 V; Note 3 8
Digital Interface (TVDD pin) absolute maximum TVDDam -0.3 4 V VSS=0 V; Note 3 8
Digital Core (VDD18 pin) absolute maximum VDD18am -0.3 2.5 V VSS=0 V; Note 3, Note 4 8
Input Current (any pin except supplies) IIN 10 mA 8
Analog Input Voltage (AIN1-4P, AIN1-4N pins) VINA -0.3 V Printed max is AVDD+0.3 V 8
Digital Input Voltage VIND -0.3 V Printed max is TVDD+0.3 V 8
Ambient Temperature (power applied, back tab connected to VSS) Ta -40 105 °C Power applied; back tab connected to VSS 8
Ambient Temperature (power applied, back tab open) Ta -40 70 °C Power applied; back tab open 8
Storage Temperature Tstg -65 150 °C 8
Analog (AVDD pin) supply AVDD 4.75 5 5.25 V LDOE pin = L (Note 5) 8
Digital Interface (TVDD pin) supply TVDD 1.7 1.8 1.98 V LDOE pin = L (Note 6) 8
Digital Core (VDD18 pin) supply VDD18 1.7 1.8 1.98 V LDOE pin = L 8
Digital Interface (TVDD pin) supply TVDD 3 3.3 3.6 V LDOE pin = H (Note 7) 8
H voltage reference VREFH1-4 4.75 5 5.25 V Note 8 8
Input Voltage (full scale) 2.7 2.8 2.9 Vpp Ta=25 C; AVDD=5.0 V; TVDD=3.3 V; fs=48 kHz; Note 10 9
S/(N+D) S/(N+D) 100 112 dB fs=48 kHz; BW=20 kHz; -1 dBFS 9
Dynamic Range 117 121 dB -60 dBFS, A-weighted; Not-Sum. mode 9
S/N (A-weighted) 117 121 dB Not-Sum. mode 9
Input Resistance 3 3.6 4.2 k Values doubled in DSD 64fs mode; DSD128/DSD256 values shown 9
Interchannel Isolation 110 120 dB AIN1-2, AIN3-4, AIN5-6, AIN7-8 9
Interchannel Gain Mismatch 0 0.5 dB 9
Power Supply Current, AVDD + VREFHm (m=1-4) 96 125 mA Normal operation; PDN pin = H; LDOE pin = H 9
Power Supply Current, TVDD (fs=48 kHz) 17 22 mA Normal operation; PDN pin = H; LDOE pin = H 9
Power Supply Current, TVDD (fs=96 kHz) 28 36 mA Normal operation; PDN pin = H; LDOE pin = H 9
Power Supply Current, TVDD (fs=192 kHz) 25 32 mA Normal operation; PDN pin = H; LDOE pin = H 9
Power Supply Current, AVDD+TVDD (power down) 10 100 A Power Down mode (PDN pin = L); Note 12 9
High-Level Input Voltage VIH 70 %TVDD TVDD=3.0-3.6 V (LDOE pin = H) 18
Low-Level Input Voltage VIL 30 %TVDD TVDD=3.0-3.6 V (LDOE pin = H) 18
High-Level Output Voltage VOH -0.5 V Iout=-100 uA; printed min is TVDD-0.5 V; TVDD=3.0-3.6 V 18
Low-Level Output Voltage (except SDA pin) VOL 0.5 V Iout=100 uA; TVDD=3.0-3.6 V 18
Low-Level Output Voltage (SDA pin) VOL 0.4 V Iout=3 mA; TVDD=3.0-3.6 V 18
High-Level Input Voltage VIH 80 %TVDD TVDD=1.7-1.98 V (LDOE pin = L) 18
Low-Level Input Voltage VIL 20 %TVDD TVDD=1.7-1.98 V (LDOE pin = L) 18
High-Level Output Voltage VOH -0.3 V Iout=-100 uA; printed min is TVDD-0.3 V; TVDD=1.7-1.98 V (LDOE pin = L) 18
Low-Level Output Voltage (except SDA pin) VOL 0.3 V Iout=100 uA; TVDD=1.7-1.98 V (LDOE pin = L) 18
Low-Level Output Voltage (SDA pin) VOL 20 %TVDD Iout=3 mA; TVDD=1.7-1.98 V (LDOE pin = L) 18
Input Leakage Current Iin 10 A 18
MCLK Frequency fCLK 2.048 49.152 MHz Ta=-40 to 105 C; AVDD=4.75-5.25 V; CL=10 pF 19
MCLK Duty Cycle dCLK 45 55 % Ta=-40 to 105 C; CL=10 pF 19
ADC Stopband (fs=48 kHz, sharp roll-off) SB 27.9 kHz SD pin=L; SLOW pin=L; Note 13 10
ADC Passband (fs=48 kHz, sharp roll-off) PB 0 22 kHz +0.001/-0.06 dB; SD pin=L; SLOW pin=L; Note 13 10
Stopband Attenuation (fs=48 kHz, sharp roll-off) SA 85 dB SD pin=L; SLOW pin=L 10
ADC Passband (fs=48 kHz, slow roll-off) PB 0 21.9 kHz +0.001/-0.076 dB; SD pin=L; SLOW pin=H; Note 13 10
ADC -6.0 dB point (fs=48 kHz, slow roll-off) PB 12.5 kHz -6.0 dB; SD pin=L; SLOW pin=H 10
ADC Stopband (fs=48 kHz, slow roll-off) SB 36.5 kHz SD pin=L; SLOW pin=H; Note 13 10
Stopband Attenuation (fs=48 kHz, slow roll-off) SA 85 dB SD pin=L; SLOW pin=H 10
ADC Passband (fs=48 kHz, short delay sharp) PB 0 22 kHz +0.001/-0.06 dB; SD pin=H; SLOW pin=L; Note 13 10
ADC Stopband (fs=48 kHz, short delay sharp) SB 27.9 kHz SD pin=H; SLOW pin=L; Note 13 10
Stopband Attenuation (fs=48 kHz, short delay sharp) SA 85 dB SD pin=H; SLOW pin=L 10
ADC Passband (fs=48 kHz, short delay slow) PB 0 21.9 kHz +0.001/-0.076 dB; SD pin=H; SLOW pin=H; Note 13 10
ADC -6.0 dB point (fs=48 kHz, short delay slow) PB 12.5 kHz -6.0 dB; SD pin=H; SLOW pin=H 10
ADC Stopband (fs=48 kHz, short delay slow) SB 36.5 kHz SD pin=H; SLOW pin=H; Note 13 10
Stopband Attenuation (fs=48 kHz, short delay slow) SA 85 dB SD pin=H; SLOW pin=H 10
ADC Passband (fs=96 kHz, sharp roll-off) PB 0 48.8 kHz +0.001/-0.06 dB; SD pin=L; SLOW pin=L; Note 13 12
ADC -6.0 dB point (fs=96 kHz, sharp roll-off) PB 44.1 kHz -6.0 dB; SD pin=L; SLOW pin=L 12
ADC Stopband (fs=96 kHz, sharp roll-off) SB 55.7 kHz SD pin=L; SLOW pin=L; Note 13 12
Stopband Attenuation (fs=96 kHz, sharp roll-off) SA 85 dB SD pin=L; SLOW pin=L 12
ADC Passband (fs=192 kHz, sharp roll-off) PB 0 100.2 kHz +0.001/-0.037 dB; SD pin=L; SLOW pin=L; Note 13 14
ADC Stopband (fs=384 kHz) SB 277.4 kHz Independent of SD and SLOW pins; Note 13 16
ADC Stopband (fs=768 kHz) SB 640.3 kHz Independent of SD and SLOW pins; Note 13 17

CAD (KiCad official)

  • Symbol: AK5578EN
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ak5578en-etched.step / ak5578en-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ak5578en.step / ak5578en.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Asahi Kasei Microdevices datasheet (72 pp, sha256 5b9b48873d5535ce, retrieved 2026-10-29, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF