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AK5534VN

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Asahi Kasei Microdevices Pre-ordered Chips, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsak5534vnfactory-2.0.0extractor-text

Verified AK5534VN

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AK5534VN · QFN-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 68-page datasheet
  • ✓distributor: lcsc C2667243, digikey 974-1122-2-ND, mouser 412-AK5534VN
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-a9rdz3mw/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.66)
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ak5534vn.kicad_sym✓ ak5534vn.kicad_mod✓ ak5534vn.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers ak5534vn: viewers · Ray 4d ago
ak5534vn-etched.glb Publish 0.1.0 · Ray 4d ago
ak5534vn-etched.step ak5534vn: factory component page (tier=lcsc) · Ray 4d ago
ak5534vn-hero.glb ak5534vn: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
ak5534vn-hero.overlay.json Publish 0.1.0 · Ray 4d ago
ak5534vn.glb Publish 0.1.0 · Ray 4d ago
ak5534vn.kicad_mod Publish 0.1.0 · Ray 4d ago
ak5534vn.kicad_sym Publish 0.1.0 · Ray 4d ago
ak5534vn.lbr Publish 0.1.0 · Ray 4d ago
ak5534vn.step Publish 0.1.0 · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
verification.json Verified: Published by the parts factory: tier lcsc, 49 pins · Ray 4d ago

AK5534VN

Asahi Kasei Microdevices · Pre-ordered Chips · QFN-48-EP(7x7)

AK5534VN from Asahi Kasei Microdevices, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal bonding; connect to AVSS.
2 VREFL1 input ADC low-level voltage reference input, normally connected to AVSS.
3 VREFH1 input ADC high-level voltage reference input, 3.0-3.6 V and not above AVDD+0.1 V.
4 AIN2N input Channel 2 negative analog input.
5 AIN2P input Channel 2 positive analog input.
6 AVDD power_in Analog power supply for AIN1-4, 3.0-3.6 V.
7 AVSS power_in Analog ground for AIN1-4.
8 AIN3P input Channel 3 positive analog input.
9 AIN3N input Channel 3 negative analog input.
10 VREFH2 input ADC high-level voltage reference input, 3.0-3.6 V and not above AVDD+0.1 V.
11 VREFL2 input ADC low-level voltage reference input, normally connected to AVSS.
12 NC unconnected No internal bonding; connect to AVSS.
13 AIN4N input Channel 4 negative analog input.
14 AIN4P input Channel 4 positive analog input.
15 TEST input Test enable pin; connect to DVSS when unused.
16 MCLK input Master clock input.
17 TVDD power_in Digital I/O buffer and LDO supply, 1.7-1.98 V (LDOE=L) or 3.0-3.6 V (LDOE=H).
18 DVSS power_in Digital ground.
19 VDD18 power_in Digital core supply input 1.7-1.98 V when LDOE=L, or LDO stabilization capacitor connection when LDOE=H.
20 PDN input Reset and power-down pin: L = reset/power down, H = normal operation.
21 PW0 input Power management and channel summation select pin 1.
22 PW1 input Power management and channel summation select pin 2.
23 PW2 input Power management and channel summation select pin 3.
24 MSN input Master/slave select pin.
25 BICK/DCLK bidirectional Audio serial data clock input (PCM slave) or output (PCM master), or DSD clock output in DSD mode; internal 100 kΩ pull-down.
26 LRCK/DSDOL1 bidirectional Channel clock input (PCM slave) or output (PCM master), or AIN1 DSD data output in DSD mode; internal 100 kΩ pull-down.
27 TDMIN/DSDOR1 bidirectional TDM data input in PCM mode or AIN2 DSD data output in DSD mode; internal 100 kΩ pull-down.
28 SDTO1/DSDOL2 output Audio serial data output for AIN1 and AIN2 in PCM mode, or AIN3 DSD output in DSD mode.
29 SDTO2/DSDOR2 output Audio serial data output for AIN3 and AIN4 in PCM mode, or AIN4 DSD output in DSD mode.
30 OVF output Analog input overflow flag output.
31 CKS0/SDA/CDTI bidirectional Clock mode select, I2C serial data I/O (SDA), or 3-wire control data input (CDTI).
32 CKS1/CAD0_I2C/CSN input Clock mode select, I2C chip address 0, or 3-wire chip select.
33 CKS2/SCL/CCLK input Clock mode select, I2C control clock (SCL), or 3-wire control clock (CCLK).
34 CKS3/CAD1 input Clock mode select or chip address 1 in I2C or 3-wire control mode.
35 SLOW/DCKB input Slow roll-off digital filter select in PCM mode, or DCLK polarity in DSD mode.
36 SD/PMOD input Short delay digital filter select in PCM mode, or DSD phase modulation mode select in DSD mode.
37 DIF0/DSDSEL0 input Audio format select in PCM mode (L: MSB justified, H: I2S), or DSD sampling rate control in DSD mode.
38 DIF1/DSDSEL1 input Audio data width select in PCM mode (L: 24-bit, H: 32-bit), or DSD sampling rate control in DSD mode.
39 TDM0 input TDM interface format select; must be fixed to L in DSD mode.
40 TDM1 input TDM interface format select; must be fixed to L in DSD mode.
41 PSN/CAD0_SPI input Control mode select (L: I2C, H: parallel, when I2C pin=H) or chip address 0 in 3-wire mode (I2C pin=L).
42 I2C input Control mode select: L = 3-wire serial, H = I2C bus or parallel control.
43 DP input DSD mode enable: L = PCM mode, H = DSD mode.
44 HPFE/DCKS input High-pass filter enable (L: disable, H: enable), or master clock frequency select in DSD mode.
45 LDOE input LDO enable (L: disable, H: enable); internal 100 kΩ pull-down.
46 ODP input Optimal data placement mode enable.
47 AIN1P input Channel 1 positive analog input.
48 AIN1N input Channel 1 negative analog input.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Asahi Kasei Microdevices
Package QFN-48-EP(7x7)
Category Interface ICs
Pins 49

CAD (KiCad official)

  • Symbol: AK5534VN
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ak5534vn-etched.step / ak5534vn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ak5534vn.step / ak5534vn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Asahi Kasei Microdevices datasheet (68 pp, sha256 273d2eeb859c2a4c, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF