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AIP74HC540SA20.TB

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Wuxi I core Elec Buffers, Drivers, Receivers, Transceivers, SOP-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AIP74HC540SA20.TB

Wuxi I core Elec · Buffers, Drivers, Receivers, Transceivers · SOP-20-300mil

AIP74HC540SA20.TB from Wuxi I core Elec, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ~{OE1} input Active-LOW output enable input; a HIGH level forces outputs Y0 to Y7 into the high-impedance OFF-state, and the outputs are enabled only when both OE1 and OE2 are LOW.
2 A0 input Data input 0 for the inverting buffer; for AiP74HC540 it uses CMOS input levels and for AiP74HCT540 TTL input levels, and the input has clamp diodes that allow current-limited interfacing above VCC.
3 A1 input Data input 1 for the inverting buffer; for AiP74HC540 it uses CMOS input levels and for AiP74HCT540 TTL input levels, and the input has clamp diodes that allow current-limited interfacing above VCC.
4 A2 input Data input 2 for the inverting buffer; for AiP74HC540 it uses CMOS input levels and for AiP74HCT540 TTL input levels, and the input has clamp diodes that allow current-limited interfacing above VCC.
5 A3 input Data input 3 for the inverting buffer; for AiP74HC540 it uses CMOS input levels and for AiP74HCT540 TTL input levels, and the input has clamp diodes that allow current-limited interfacing above VCC.
6 A4 input Data input 4 for the inverting buffer; for AiP74HC540 it uses CMOS input levels and for AiP74HCT540 TTL input levels, and the input has clamp diodes that allow current-limited interfacing above VCC.
7 A5 input Data input 5 for the inverting buffer; for AiP74HC540 it uses CMOS input levels and for AiP74HCT540 TTL input levels, and the input has clamp diodes that allow current-limited interfacing above VCC.
8 A6 input Data input 6 for the inverting buffer; for AiP74HC540 it uses CMOS input levels and for AiP74HCT540 TTL input levels, and the input has clamp diodes that allow current-limited interfacing above VCC.
9 A7 input Data input 7 for the inverting buffer; for AiP74HC540 it uses CMOS input levels and for AiP74HCT540 TTL input levels, and the input has clamp diodes that allow current-limited interfacing above VCC.
10 GND power_in Ground (0V) reference for all voltages on the device.
11 Y7 tri_state Inverting 3-state data output 7, which goes high-impedance when either output enable is HIGH and is rated for an output current of ±35 mA (absolute maximum).
12 Y6 tri_state Inverting 3-state data output 6, which goes high-impedance when either output enable is HIGH and is rated for an output current of ±35 mA (absolute maximum).
13 Y5 tri_state Inverting 3-state data output 5, which goes high-impedance when either output enable is HIGH and is rated for an output current of ±35 mA (absolute maximum).
14 Y4 tri_state Inverting 3-state data output 4, which goes high-impedance when either output enable is HIGH and is rated for an output current of ±35 mA (absolute maximum).
15 Y3 tri_state Inverting 3-state data output 3, which goes high-impedance when either output enable is HIGH and is rated for an output current of ±35 mA (absolute maximum).
16 Y2 tri_state Inverting 3-state data output 2, which goes high-impedance when either output enable is HIGH and is rated for an output current of ±35 mA (absolute maximum).
17 Y1 tri_state Inverting 3-state data output 1, which goes high-impedance when either output enable is HIGH and is rated for an output current of ±35 mA (absolute maximum).
18 Y0 tri_state Inverting 3-state data output 0, which goes high-impedance when either output enable is HIGH and is rated for an output current of ±35 mA (absolute maximum).
19 ~{OE2} input Active-LOW output enable input; a HIGH level forces outputs Y0 to Y7 into the high-impedance OFF-state, and the outputs are enabled only when both OE1 and OE2 are LOW.
20 VCC power_in Supply voltage; for AiP74HC540 the recommended range is 2.0 V to 6.0 V and the absolute maximum is 7.0 V.

Key specifications

Parameter Value
Manufacturer Wuxi I core Elec
Package SOP-20-300mil
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 2 5 6 V 8
input voltage VI 0 V 8
output voltage VO 0 V 8
input transition rise and fall rate Δt/ΔV 625 ns/V VCC=2.0V 8
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC=4.5V 8
input transition rise and fall rate Δt/ΔV 83 ns/V VCC=6.0V 8
ambient temperature Tamb -40 105 ℃ 8
supply voltage VCC -0.5 7 V 8
input clamping current IIK -20 20 mA VI < -0.5V or VI > VCC+0.5V 8
output clamping current IOK -20 20 mA VO < -0.5V or VO > VCC+0.5V 8
output current IO -35 35 mA -0.5V < VO < VCC+0.5V 8
supply current ICC 70 mA 8
ground current IGND -70 mA 8
storage temperature Tstg -65 150 ℃ 8
total power dissipation Ptot 500 mW SOP20 package; above 70℃ derates 8mW/K (note [2]) 8
soldering temperature TL 250 ℃ 10s, SOP 8
HIGH-level input voltage VIH 1.5 V VCC=2.0V; Tamb=-40℃ to +105℃ 11
HIGH-level input voltage VIH 3.15 V VCC=4.5V; Tamb=-40℃ to +105℃ 11
HIGH-level input voltage VIH 4.2 V VCC=6.0V; Tamb=-40℃ to +105℃ 11
LOW-level input voltage VIL 0.5 V VCC=2.0V; Tamb=-40℃ to +105℃ 11
LOW-level input voltage VIL 1.35 V VCC=4.5V; Tamb=-40℃ to +105℃ 11
LOW-level input voltage VIL 1.8 V VCC=6.0V; Tamb=-40℃ to +105℃ 11
HIGH-level output voltage VOH 1.9 V VI = VIH or VIL; IO=-20uA; VCC=2.0V; Tamb=-40℃ to +105℃ 11
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO=-20uA; VCC=4.5V; Tamb=-40℃ to +105℃ 11
HIGH-level output voltage VOH 5.9 V VI = VIH or VIL; IO=-20uA; VCC=6.0V; Tamb=-40℃ to +105℃ 11
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO=-6.0mA; VCC=4.5V; Tamb=-40℃ to +105℃ 11
HIGH-level output voltage VOH 5.2 V VI = VIH or VIL; IO=-7.8mA; VCC=6.0V; Tamb=-40℃ to +105℃ 11
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO=20uA; VCC=2.0V; Tamb=-40℃ to +105℃ 11
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; IO=6.0mA; VCC=4.5V; Tamb=-40℃ to +105℃ 11
input leakage current II -1 1 uA VI=VCC or GND; VCC=6.0V; Tamb=-40℃ to +105℃ 11
OFF-state output current IOZ -10 10 uA VI=VIH or VIL; VCC=6.0V; VO=VCC or GND; Tamb=-40℃ to +105℃ 11
supply current ICC 160 uA VI=VCC or GND; IO=0A; VCC=6.0V; Tamb=-40℃ to +105℃ 11
An to Yn propagation delay tpd 150 ns VCC=2.0V; CL=50pF; see Figure 6; Tamb=-40℃ to +105℃ 14
An to Yn propagation delay tpd 30 ns VCC=4.5V; CL=50pF; see Figure 6; Tamb=-40℃ to +105℃ 14
An to Yn propagation delay tpd 26 ns VCC=6.0V; CL=50pF; see Figure 6; Tamb=-40℃ to +105℃ 14
OE-n to Yn enable time ten 240 ns VCC=2.0V; CL=50pF; see Figure 7; Tamb=-40℃ to +105℃ 14
OE-n to Yn enable time ten 48 ns VCC=4.5V; CL=50pF; see Figure 7; Tamb=-40℃ to +105℃ 14
OE-n to Yn enable time ten 41 ns VCC=6.0V; CL=50pF; see Figure 7; Tamb=-40℃ to +105℃ 14
OE-n to Yn disable time tdis 240 ns VCC=2.0V; CL=50pF; see Figure 7; Tamb=-40℃ to +105℃ 14
OE-n to Yn disable time tdis 48 ns VCC=4.5V; CL=50pF; see Figure 7; Tamb=-40℃ to +105℃ 14
OE-n to Yn disable time tdis 41 ns VCC=6.0V; CL=50pF; see Figure 7; Tamb=-40℃ to +105℃ 14
transition time tt 90 ns VCC=2.0V; CL=50pF; see Figure 6; Tamb=-40℃ to +105℃ 14
transition time tt 18 ns VCC=4.5V; CL=50pF; see Figure 6; Tamb=-40℃ to +105℃ 14
transition time tt 15 ns VCC=6.0V; CL=50pF; see Figure 6; Tamb=-40℃ to +105℃ 14
An to Yn propagation delay tpd 30 100 ns VCC=2.0V; CL=50pF; see Figure 6; Tamb=25℃ 12
An to Yn propagation delay tpd 11 20 ns VCC=4.5V; CL=50pF; see Figure 6; Tamb=25℃ 12
An to Yn propagation delay tpd 9 17 ns VCC=6.0V; CL=50pF; see Figure 6; Tamb=25℃ 12

CAD (KiCad official)

  • Symbol: AIP74HC540SA20.TB
  • Footprint: Package_SO:SOP-20_7.5x12.8mm_P1.27mm
  • 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: aip74hc540sa20-tb-etched.step / aip74hc540sa20-tb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aip74hc540sa20-tb.step / aip74hc540sa20-tb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I core Elec datasheet (20 pp, sha256 57b6753a0e3aa53e, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF