AiP74HC165SA16.TR

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  "slug": "aip74hc165sa16-tr",
  "title": "AiP74HC165SA16.TR",
  "brief": "Wuxi I core Elec Shifting Register, SOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
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  "component": {
    "mpn": "AiP74HC165SA16.TR",
    "manufacturer": "Wuxi I core Elec",
    "package": "SOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shifting Register",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2309141130_Wuxi-I-core-Elec-AiP74HC165SA16-TR_C5139324.pdf",
    "parts": {
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      "footprint": "aip74hc165sa16-tr.kicad_mod",
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      "model_3d_plain": "aip74hc165sa16-tr.glb",
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      "model_3d_step_plain": "aip74hc165sa16-tr.step",
      "lbr": "aip74hc165sa16-tr.lbr"
    },
    "distributor_links": {
      "lcsc": "C5139324"
    },
    "pins": [
      {
        "number": "1",
        "name": "PL",
        "type": "input",
        "description": "Asynchronous parallel load input, active low. When PL=L, data on D0-D7 is loaded into the shift register regardless of CP."
      },
      {
        "number": "2",
        "name": "CP",
        "type": "input",
        "description": "Clock input, low-to-high edge triggered. Shifts serial data through the register when CE is low and PL is high."
      },
      {
        "number": "3",
        "name": "D4",
        "type": "input",
        "description": "Parallel data input bit 4 (Dn). Loaded into the corresponding shift-register stage when PL is low."
      },
      {
        "number": "4",
        "name": "D5",
        "type": "input",
        "description": "Parallel data input bit 5 (Dn). Loaded into the corresponding shift-register stage when PL is low."
      },
      {
        "number": "5",
        "name": "D6",
        "type": "input",
        "description": "Parallel data input bit 6 (Dn). Loaded into the corresponding shift-register stage when PL is low."
      },
      {
        "number": "6",
        "name": "D7",
        "type": "input",
        "description": "Parallel data input bit 7 (Dn). Last stage that appears at Q7 after a parallel load."
      },
      {
        "number": "7",
        "name": "/Q7",
        "type": "output",
        "description": "Complementary serial output of the last (Q7) stage. Inverse of the Q7 pin."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V)."
      },
      {
        "number": "9",
        "name": "Q7",
        "type": "output",
        "description": "Serial output from the last (Q7) stage of the shift register."
      },
      {
        "number": "10",
        "name": "DS",
        "type": "input",
        "description": "Serial data input. Shifted into stage Q0 on each CP rising edge while CE is low and PL is high."
      },
      {
        "number": "11",
        "name": "D0",
        "type": "input",
        "description": "Parallel data input bit 0 (Dn). Loaded into the corresponding shift-register stage when PL is low."
      },
      {
        "number": "12",
        "name": "D1",
        "type": "input",
        "description": "Parallel data input bit 1 (Dn). Loaded into the corresponding shift-register stage when PL is low."
      },
      {
        "number": "13",
        "name": "D2",
        "type": "input",
        "description": "Parallel data input bit 2 (Dn). Loaded into the corresponding shift-register stage when PL is low."
      },
      {
        "number": "14",
        "name": "D3",
        "type": "input",
        "description": "Parallel data input bit 3 (Dn). Loaded into the corresponding shift-register stage when PL is low."
      },
      {
        "number": "15",
        "name": "CE",
        "type": "input",
        "description": "Clock enable input, active low. When CE is low the clock is enabled; a high on CE inhibits (gates off) the CP input."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage. AiP74HC165: 2.0-6.0 V (5.0 V typ). AiP74HCT165: 4.5-5.5 V (5.0 V typ). Absolute max +7 V."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2309141130_Wuxi-I-core-Elec-AiP74HC165SA16-TR_C5139324.pdf",
        "pages": 25,
        "sha256": "0c8af9520508e3e0",
        "source_tier": "lcsc"
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      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -4.445
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74HC165",
      "logic_family": "74HC",
      "function_code": "165",
      "function_class": "ShiftRegister",
      "function_name": "8-Bit PISO Shift Register",
      "manufacturer": "Wuxi I-core Elec",
      "is_specialty": false
    },
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        "extents_mm": [
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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        "zmin_mm": 0,
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        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Wuxi I core Elec",
      "Package": "SOP-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "sections": [
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  "discovery_pitch": "AiP74HC165SA16.TR (Wuxi I core Elec) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
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  "updated_at": "2026-09-24T16:11:44.029Z"
}