AI Flow: Reverse Engineering

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It starts with four photos of a motor driver board, and one request.

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Find the parts, the functional blocks, the pours and the routing.

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Copy everything you can see.

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Then work out what you can't, pick a layer count, and say how sure you are.

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The first attempt reused the existing AI Flow program, and Caleb called that

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out.

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So this became its own Rust program, with its own copper reader and its own

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router.

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The program does the measuring. The AI does the naming.

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Eleven steps, and each one records what it produced.

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Two photos of the top, two of the bottom.

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The program finds the board edge in each one and straightens it.

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Then it turns the bottom over to line up with the top. 38 holes agree, 2

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don't.

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Scale comes from the board itself. The header rows have known pitches, 2 mm

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and 2.54 mm.

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That gives 46.6 pixels per millimeter.

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The driver chip's 6 mm body settles which pitch standard the rows are.

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Then the parts, 137 of them.

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103 are placed by their own pads on the photo.

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Markings get read where they're legible, like this TI DRV8323S.

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Where they aren't, the program says so. 91 parts still need a test.

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Silkscreen and circuit role sort them into 11 blocks.

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Power entry, the three-phase power stage, bridge sensing, the logic supply.

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The gate driver, the microcontroller, CAN, AUX, the fan, motor temperature and

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the mounting holes.

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Then came the real miss. The first copy had 58 pours, all on the bottom, and

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not a single track.

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Caleb looked at it and said fill and via recognition was completely lacking.

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That was correct.

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So the reader was rewritten. Under solder mask, copper looks a little lighter

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than bare laminate, compared with its own neighborhood.

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Thin dark lines mark the gaps between copper.

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Follow those gaps and the board falls apart into islands. 1,444 of them.

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That became 116 pours and 314 tracks, on both faces.

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Vias are next. 2,681 candidates, and 1,028 kept.

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They're tented on the top, so only 45 show on both faces.

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Zoom in and the misses show. Up to a third land on something pale, mostly

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silkscreen letters and lines.

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And the 3 read as leading only inward look like ordinary domes in a stitching

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field. So that's no proof of inner layers.

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All of that goes straight into a KiCad board, as photographed, before anything

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is guessed.

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Here's the copy laid over the top photo, and over the bottom.

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Now for what nobody can see. Datasheets and the circuit fill in the rest of

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the nets. 77 nets, 249 connections to make.

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99 pins disagree with the copper they seem to touch. Those get reported, not

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quietly fixed.

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Then the router. It's written for this job, and it uses every inner layer.

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When photographed pours were hard walls, 235 connections stayed open.

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Real vias pass through pours, so seen copper became expensive to cross instead

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of forbidden.

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17 recorded runs later, 6 and 8 layers are down to about 30.

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The layer count comes from how hard that is.

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4 layers: 54 open, and 327 mm cut through copper the photos show.

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6 layers: 34 open, 24 mm.

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8 layers: 29 open, 30 mm. That's no real gain, since runs vary by about a

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quarter.

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So the proposal is 6. It's a measure of difficulty. Nobody has seen inside

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this board.

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The rules were set from the start: KiCad's defaults, 0.2 mm track and

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clearance.

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Most of what's left open is fan-out at the two QFN chips.

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The same copy at JLC-style rules, 0.127 mm, leaves just 2 open at 6 layers.

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So that's mostly a rules limit. That run has no valid design rule check yet.

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Then it reviews itself, in a loop. 4 passes, and the last one changes nothing.

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Blocks and placement come out high. Identity, values, copper, vias and layers,

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medium.

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Connectivity is low, and it says why.

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Everything still unknown gets a test. 119 of them.

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So this is not a finished board.

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34 connections stay open. KiCad counts 76 missing, because some seen copper

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isn't joined in the copy.

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The rails at the upper left of the bottom are largely missing, and signal

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bundles mostly read as gaps.

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And the inner copper is one way to connect it, not what's actually inside.

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Every stage is saved in the flow window. 110 recorded steps you can replay.

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From the first prompt to the report took about 6.5 hours of AI time, with idle

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gaps over 15 minutes cut out.

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914,981 output tokens, and 272 million cache reads, across 463 model calls.

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Next up: real measurements on this board, and a second board, before any of it

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goes public.