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AI Flow: Reverse Engineering
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Photos of a PCB to a tagged KiCad copy: parts placed, copper and nets with their evidence, a schematic, a measured confidence score, bench tests and a video of the run.
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Add the page README, the run and process video sub-pages, and captions
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README.md+111−1@@ -1,3 +1,113 @@ # AI Flow: Reverse Engineering -Photos of a PCB to a tagged KiCad copy with its traced copper, a layer-count proposal and the tests that settle what the photos cannot show.+::adom-video{src="/adom/ai-flow-reverse-engineering/render/videos/driver-re2-process.video.json"}++Photos of a PCB in, a KiCad copy out: the parts identified, the functional blocks named, every island of copper traced from the photos, the connections nobody can see routed, a layer count proposed from how hard that was, a confidence statement, and the tests that would settle what is still unknown.++It is a standalone Rust program. It measures from the photos, generates the board, routes and checks. The AI running it supplies what takes judgement: what a part is, what a block does, what a net is called. Every claim carries an evidence tag: `SEEN`, `MEASURED`, `DATASHEET`, `INFERRED` or `UNKNOWN`.++**Status: under test on one board, not a finished result.** No stackup closes every connection at default rules, up to a third of the kept vias look false, and nothing has been checked against a real netlist, stackup or X-ray. [docs/status.md](docs/status.md) lists every known gap.++## Results on the Driver board++The test case is a three-phase BLDC motor controller, 73.65 x 61.78 mm, from four photos and nothing else. All figures use KiCad's default rules.++| Item | Result |+|---|---|+| Parts | 137 placed, 103 by their own pads on the photo, 91 with something still inferred or unknown |+| Blocks | 11 |+| Copper | 116 pours and 314 tracks on both faces, from 1,444 islands |+| Vias | 1,028 kept of 2,681 candidates. Up to 338 land on silkscreen or other pale pixels and look false |+| Nets | 77, with 249 connections to make. 99 pins disagree with the copper they appear to touch |+| Review | 4 passes, the last changing nothing. Connectivity is low confidence |+| Tests | 119, settling 1,632 open items |++| Layers | Open of 249 | New DRC errors | Crossing seen copper |+|---|---|---|---|+| 4 | 54 | 17 | 327 mm |+| **6 (proposed)** | **34** | **6** | **24 mm** |+| 8 | 29 | 9 | 30 mm |++The 6 comes from routing difficulty only. The photos prove no minimum layer count, and repeat runs of one stackup vary by about a quarter. The same copy at JLC-style rules (0.127 mm) leaves 2 open at 6 layers, but the shared KiCad service can't check those rules, so that run has no valid DRC.++## Driver board run: every file from the test++<table>+<tr>+<td width="104"><a href="runs/driver-re2/README.md"><img src="runs/driver-re2/driver-re2-icon.jpg" width="112" alt="Driver board run"></a><br><sub> Driver run </sub></td>+<td>The full result of the Driver board test: the report, the evidence pictures, the KiCad copy and each routed stackup. Read it to judge the flow on a real board, including what it got wrong. You can open the boards in KiCad and check any measurement against the photos.<br><br><strong><a href="runs/driver-re2/README.md">Open the run</a></strong></td>+</tr>+</table>++## Process video: how it was made++<table>+<tr>+<td width="104"><a href="docs/process-video/README.md"><img src="docs/process-video/process-video-icon.jpg" width="112" alt="Process video"></a><br><sub> Process video </sub></td>+<td>The source of each scene in the video above, the full voice-over script and the tools that built it. It matters because nothing was filmed live, so this page says what each shot really is. Use it to check a claim or re-cut a scene.<br><br><strong><a href="docs/process-video/README.md">Read how it was made</a></strong>, or get the <a href="videos/driver-re2-process.vtt">VTT</a> or <a href="videos/driver-re2-process.srt">SRT</a> captions</td>+</tr>+</table>++## Install and run++```bash+adom-wiki pkg install adom/ai-flow-reverse-engineering # or ./build.sh from the source, which needs Rust+adom-wiki pkg install adom/service-kicad adom/adom-2dboard adom/adom-schematic++mkdir my-board && cd my-board+adom-aiflow-reverse init --top a.jpg b.jpg --bottom c.jpg --rules kicad-default --ai-thread me+adom-aiflow-reverse serve --port 8891 & # the flow window: open this in a browser and leave it open+adom-aiflow-reverse next # always says what to do now+```++`next` walks the run. `steps` shows every stage and whether it is done, stale or next. An edit to an earlier artifact makes the later stages stale, and the flow window draws the loop back.++## The stages++| Stage | What happens | Who decides |+|---|---|---|+| intake | Finds the outline, straightens each photo, measures sharpness, plated holes and hole rows | program |+| scale | Pixels per mm from standard hole pitches, with one part body from a datasheet to pick the pitch standard; aligns bottom to top on shared holes | program, AI names the body |+| parts | Finds bodies, matches packages, then snaps each footprint's pads onto the metal in the photo | program measures, AI reads markings |+| blocks | Proposes groups of parts that sit together | AI names them |+| copper | Traces every island of copper on both faces into pours, tracks and vias | program |+| mimic | Writes the KiCad project with everything visible | program |+| snapshot | Saves the copy as it stands, before anything is inferred | program |+| connect | Routes what is hidden, jumping the layer count until it closes and the DRC passes; proposes the stackup | program, AI adds datasheet nets |+| review | Re-measures everything in a loop until a pass changes nothing; states confidence per category | AI, from the measurements |+| tests | One test for every `INFERRED` or `UNKNOWN` item | program lists, AI writes the method |+| report | The whole result with its evidence | program |++Each stage records its interactive PCB or schematic in the flow window, numbered and never overwritten, so the window replays the whole process afterwards.++## Rules are set at the start++`init --rules` takes a named profile or a JSON file. The same values drive the zones, the router and the gate, so nothing is checked against a rule it was not built to.++| Profile | Use |+|---|---|+| `kicad-default` | KiCad's own defaults, which is what the shared KiCad service applies to a lone board |+| `jlc-4l` | JLCPCB 4-layer capabilities. The gate needs a native `kicad-cli`, because the shared service does not read a project's rules |++## What it writes++```+kicad/<name>.kicad_pcb, .kicad_sch, .kicad_pro the copy+reverse-flow/parts.json blocks.json copper.json nets.json layers.json review.json tests.json+reverse-flow/report.md the result+reverse-flow/routes/L<n>/ one folder per stackup tried: routed.json, board, DRC reports, gate.json+reverse-flow/evidence/ overlays to check every measurement by eye+reverse-flow/views/ the recorded PCB and schematic views+```++## How the copper is read and the board is routed++[docs/method.md](docs/method.md) explains the measurements and why each works. Read it before changing `trace.rs`, `islands.rs` or `route.rs`.++## Contributing++Run `cargo test --release` before a change and look at `evidence/copper-islands-*.jpg` after one. Thresholds that came from measuring photos say so where they are defined; if you change one, measure it on more than one board. Tests in each module show the behaviour it must keep.++## License++MIT. The timeline page in `assets/` is copied from `adom/adom-aiflow` (MIT, Adom Industries).
runs/driver-re2/README.mdadded+103@@ -0,0 +1,103 @@+# Driver board: reverse engineered from photos++Run of adom-aiflow-reverse 0.2 on Driver1.JPG to Driver4.jpg only, updated 2026-11-04. The generated tables (evidence counts, every open item, the tests) are in [report-tables.md](data/report-tables.md).++**Result: a 6-layer proposal, with copper traced from the photos on both faces. No stackup closes every connection at KiCad default rules, so this is not a finished board.** 34 of 249 connections stay open at 6 layers, nearly all fan-outs at the two QFNs.++## What the board is++A three-phase BLDC motor controller, 73.65 x 61.78 mm with 2.5 mm corners. A TI DRV8323S gate driver (marking read, confirmed against TI's product page) drives six TDSON-8 MOSFETs in three half-bridges to the X1, X2 and X3 lugs, with 2 mΩ shunts (R002) on the low sides. An STM32G4 (silkscreen; package marking unreadable) controls it. Logic power comes through a Schottky (SS210) from VIN into an 8-pin SOT-23 buck with a 100 µH inductor, then two adjustable SOT-223 regulators whose dividers give 4.48 V and 3.28 V. The board also has CAN (SOIC-8 transceiver, terminal blocks, header, termination jumper), an AUX port, an SPI or I2C expansion header, a 4-pin fan header, a motor NTC input, SWD and a reset button.++## The photos and the copy++| | Top | Bottom (turned over to line up with the top) |+|---|---|---|+| Photo |  |  |+| Copper islands read |  |  |+| Copy over the photo |  |  |+| Copy in the viewer |  |  |++## How it was measured++| Step | Result |+|---|---|+| Photos | Outline found in all four photos (connectors over the edge left out of the fit); bottom turned over top-to-bottom (38 holes agree, 2 disagree) |+| Scale | 46.599 px/mm from the 2.0 and 2.54 mm header rows. The DRV8323S body (6 x 6 mm, TI; it measures 41 px/mm) only picks the pitch standard, so the number rests on the holes alone. Bottom aligned to top on 40 holes, 0.204 mm residual |+| 1 Parts | 137 parts. 103 placed by their own pads on the photo, 12 from a body or plated-hole centre, the rest by direct reading. 673 detected candidates all accounted for |+| 2 Blocks | 11 blocks from silkscreen and topology |+| 3 Copper | 1444 islands read from the photos: 116 pours and 314 tracks on the board, 1028 vias kept of 2681 candidates, up to 338 of them likely false, on silkscreen or other pale pixels |+| 4 Copy | KiCad board with the traced pours filled as photographed. 146 DRC errors before routing: 62 courtyard overlaps, 59 clearance, 30 board edge, 3 solder mask bridge, 1 hole in a courtyard |+| 5 Connections | 77 nets, completed from TI SLVSDJ3D (DRV8323S pins), KiCad's ST-derived STM32G431 symbol and inference. 99 pins disagree with the copper they appear to touch and are reported, not applied |+| 5 Layers | **6 proposed.** See below |+| 6 Review | 4 passes; the last changed nothing |+| 7 Tests | 119 tests covering the open items |++## Layer count++Rules: KiCad default (0.2 mm track and clearance, 0.6/0.3 mm via, 0.5 mm edge), set at the start and used by the zones, router and DRC.++| Layers | Open of 249 | New DRC errors | Missing per KiCad | Crossing seen copper |+|---|---|---|---|---|+| 4 | 54 | 17 | 84 | 327 mm |+| **6** | **34** | **6** | **76** | **24 mm** |+| 8 | 29 | 9 | 69 | 30 mm |++The evidence for 6 is routing difficulty. At 4 layers the router has to cut 327 mm through copper the photos show; at 6 that falls to 24 mm, and 8 adds nothing. Routing the same stackup again varies by about a quarter (6 layers: 25 to 34 open), so 6 and 8 are not distinguishable on open connections. The photos prove no minimum: the 3 vias read as leading only inward look like ordinary domes in a stitching field. The layer count has not been seen directly: T-layers settles it.++The open connections are a rules limit more than a layer limit. The same copy routed at JLC 4-layer capabilities (0.127 mm track and clearance, 0.45/0.2 mm via) leaves 30 open at 4 layers and **2 at 6**. KiCad's shared service checks only its default rules, so that run has no valid DRC. It is in [routes/jlc-experiment](routes/jlc-experiment).++Inner layers proposed: In1 GND, In4 +3V3 (both INFERRED, as the largest power nets), In2 and In3 signals. The routed copper is one possible way to make the connections, not what is inside the board.++| 4 layers, routed inner copper | 6 layers, routed inner copper |+|---|---|+|  |  |++## Confidence (last review pass)++| Category | Level | Why |+|---|---|---|+| identity | Medium | DRV8323S, SS210 diodes, R002 shunts, the 100 uH inductor and every connector are read off the photo; the MOSFETs, the STM32G4 variant, the buck IC and the CAN transceiver rest on package and circuit role |+| values | Medium | Resistor codes read where legible; every MLCC value and ten resistor codes are not readable |+| blocks | High | Silkscreen labels and part identities agree with the block topology |+| placement | High | 103 of 137 parts placed by their own pads on the photo; 62 courtyard overlaps and 23 pad-to-pad clearance errors remain |+| copper | Medium | Phase, VIN and ground pours and the via fields follow the photos by eye. See the misses below |+| vias | Medium at the last pass, too high | Up to 338 of the 1028 land on pale pixels, mostly silkscreen letters and lines, and look false. Only 45 are confirmed on both faces, because vias tent on the top. Sizes are the rule's, not measured |+| layers | Medium | From routing difficulty. Never seen directly |+| connectivity | Low | The ring test does not reliably separate a joined plated pad from an isolated one on these photos; 827 mm2 of pour and 94 mm of track have no net; the MCU pin map and passive roles are inferred |++## Not done++- **34 connections stay open at 6 layers**, and KiCad reports 76 missing, because some seen copper of one net is not joined in the copy.+- **The bottom's upper-left rails are largely missing** from the copy. The photo is darker there and the islands fragment.+- **The bottom's signal bundles** come out mostly as gaps in the pour, not separate tracks. 637 short fragments were dropped as misreadings.+- **False vias.** Up to 338 kept vias sit on silkscreen or other pale pixels. They feed net assignment and block the router, so the net and layer results are less certain than the tables suggest.+- **The router does not yet claim copper of unknown net.** It pays to cross it where it could be following it.+- **Refilling zones in KiCad** will flood the traced pours; the written fill is the measured one.++## The via problem++Blue-green circles are kept vias. Red circles land on pale pixels, meaning a 0.35 mm patch more than a quarter pale. That is a rough screen, not an exact count: most are on silkscreen letters and lines, and some on bright copper edges.++++The 3 vias read as leading only inward, on both photos. The red ring marks each one. Two sit in a field of ordinary domes, and the third is a dome beside a group of tracks.++++## Grading against the 2026-11-02 hand-made reverse engineering (reference only, not input)++That earlier work is not the truth either, so agreement shows only that two readings match.++- 96 percent of the earlier board's parts matched by position, median offset 0.46 mm, 110 rotations agree.+- 86 percent of the pin pairs this run puts on one net share a net there too (weighted by the large GND and VIN nets).+- Layer count differs: 6 here, 4 there. The earlier board's 4 left 27 nets to route by hand, so it did not close either.+- Disagreements to settle with the tests: the gate-driver passives (0805 here, 0603 there), the JST connector position, four small plated holes found only here.++## Files++| Path | What it is |+|---|---|+| [kicad/](kicad) | The delivered copy, routed at 6 layers: board, schematic, project |+| [routes/](routes) | The routed board, DRC, gate and log for 4, 6 and 8 layers, plus the JLC experiment |+| [data/](data) | parts, blocks, copper, nets, layers, review, tests and the report as generated |+| [images/](images) | The pictures on this page, reduced for the web |
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videos/driver-re2-process.srtadded+328@@ -0,0 +1,328 @@+1+00:00:01,952 --> 00:00:05,849+It starts with four photos of a motor driver board, and one request.++2+00:00:05,869 --> 00:00:10,135+Find the parts, the functional blocks, the pours and the routing.++3+00:00:10,155 --> 00:00:11,794+Copy everything you can see.++4+00:00:11,814 --> 00:00:15,780+Then work out what you can't, pick a layer count, and say how sure you are.++5+00:00:16,361 --> 00:00:21,041+The first attempt reused the existing AI Flow program, and Caleb called that++6+00:00:21,061 --> 00:00:21,288+out.++7+00:00:21,308 --> 00:00:25,908+So this became its own Rust program, with its own copper reader and its own++8+00:00:25,928 --> 00:00:26,339+router.++9+00:00:26,359 --> 00:00:29,894+The program does the measuring. The AI does the naming.++10+00:00:29,914 --> 00:00:33,128+Eleven steps, and each one records what it produced.++11+00:00:33,690 --> 00:00:35,968+Two photos of the top, two of the bottom.++12+00:00:35,988 --> 00:00:39,805+The program finds the board edge in each one and straightens it.++13+00:00:39,825 --> 00:00:44,512+Then it turns the bottom over to line up with the top. 38 holes agree, 2++14+00:00:44,532 --> 00:00:44,904+don't.++15+00:00:45,482 --> 00:00:51,031+Scale comes from the board itself. The header rows have known pitches, 2 mm++16+00:00:51,051 --> 00:00:51,923+and 2.54 mm.++17+00:00:51,943 --> 00:00:55,113+That gives 46.6 pixels per millimeter.++18+00:00:55,133 --> 00:00:59,787+The driver chip's 6 mm body settles which pitch standard the rows are.++19+00:01:00,360 --> 00:01:02,841+Then the parts, 137 of them.++20+00:01:02,861 --> 00:01:06,374+103 are placed by their own pads on the photo.++21+00:01:06,394 --> 00:01:12,507+Markings get read where they're legible, like this TI DRV8323S.++22+00:01:12,527 --> 00:01:16,699+Where they aren't, the program says so. 91 parts still need a test.++23+00:01:17,284 --> 00:01:20,918+Silkscreen and circuit role sort them into 11 blocks.++24+00:01:20,938 --> 00:01:26,152+Power entry, the three-phase power stage, bridge sensing, the logic supply.++25+00:01:26,172 --> 00:01:31,719+The gate driver, the microcontroller, CAN, AUX, the fan, motor temperature and++26+00:01:31,739 --> 00:01:33,074+the mounting holes.++27+00:01:33,658 --> 00:01:38,749+Then came the real miss. The first copy had 58 pours, all on the bottom, and++28+00:01:38,769 --> 00:01:40,026+not a single track.++29+00:01:40,046 --> 00:01:44,773+Caleb looked at it and said fill and via recognition was completely lacking.++30+00:01:44,793 --> 00:01:45,676+That was correct.++31+00:01:46,249 --> 00:01:50,301+So the reader was rewritten. Under solder mask, copper looks a little lighter++32+00:01:50,321 --> 00:01:53,209+than bare laminate, compared with its own neighborhood.++33+00:01:53,229 --> 00:01:56,060+Thin dark lines mark the gaps between copper.++34+00:01:56,080 --> 00:02:02,294+Follow those gaps and the board falls apart into islands. 1,444 of them.++35+00:02:02,314 --> 00:02:07,370+That became 116 pours and 314 tracks, on both faces.++36+00:02:07,949 --> 00:02:13,882+Vias are next. 2,681 candidates, and 1,028 kept.++37+00:02:13,902 --> 00:02:18,031+They're tented on the top, so only 45 show on both faces.++38+00:02:18,051 --> 00:02:22,994+Zoom in and the misses show. Up to a third land on something pale, mostly++39+00:02:23,014 --> 00:02:24,965+silkscreen letters and lines.++40+00:02:24,985 --> 00:02:29,825+And the 3 read as leading only inward look like ordinary domes in a stitching++41+00:02:29,845 --> 00:02:32,477+field. So that's no proof of inner layers.++42+00:02:33,050 --> 00:02:37,964+All of that goes straight into a KiCad board, as photographed, before anything++43+00:02:37,984 --> 00:02:38,659+is guessed.++44+00:02:38,679 --> 00:02:41,979+Here's the copy laid over the top photo, and over the bottom.++45+00:02:42,550 --> 00:02:48,074+Now for what nobody can see. Datasheets and the circuit fill in the rest of++46+00:02:48,094 --> 00:02:51,252+the nets. 77 nets, 249 connections to make.++47+00:02:51,272 --> 00:02:56,221+99 pins disagree with the copper they seem to touch. Those get reported, not++48+00:02:56,241 --> 00:02:57,136+quietly fixed.++49+00:02:57,726 --> 00:03:02,040+Then the router. It's written for this job, and it uses every inner layer.++50+00:03:02,060 --> 00:03:06,974+When photographed pours were hard walls, 235 connections stayed open.++51+00:03:06,994 --> 00:03:11,990+Real vias pass through pours, so seen copper became expensive to cross instead++52+00:03:12,010 --> 00:03:12,826+of forbidden.++53+00:03:12,846 --> 00:03:17,587+17 recorded runs later, 6 and 8 layers are down to about 30.++54+00:03:18,157 --> 00:03:21,244+The layer count comes from how hard that is.++55+00:03:21,264 --> 00:03:27,699+4 layers: 54 open, and 327 mm cut through copper the photos show.++56+00:03:27,719 --> 00:03:30,646+6 layers: 34 open, 24 mm.++57+00:03:30,666 --> 00:03:37,037+8 layers: 29 open, 30 mm. That's no real gain, since runs vary by about a++58+00:03:37,057 --> 00:03:37,737+quarter.++59+00:03:37,757 --> 00:03:42,411+So the proposal is 6. It's a measure of difficulty. Nobody has seen inside++60+00:03:42,431 --> 00:03:43,105+this board.++61+00:03:43,693 --> 00:03:48,776+The rules were set from the start: KiCad's defaults, 0.2 mm track and++62+00:03:48,796 --> 00:03:49,516+clearance.++63+00:03:49,536 --> 00:03:53,723+Most of what's left open is fan-out at the two QFN chips.++64+00:03:53,743 --> 00:04:00,570+The same copy at JLC-style rules, 0.127 mm, leaves just 2 open at 6 layers.++65+00:04:00,590 --> 00:04:05,024+So that's mostly a rules limit. That run has no valid design rule check yet.++66+00:04:05,592 --> 00:04:10,631+Then it reviews itself, in a loop. 4 passes, and the last one changes nothing.++67+00:04:10,651 --> 00:04:15,930+Blocks and placement come out high. Identity, values, copper, vias and layers,++68+00:04:15,950 --> 00:04:16,406+medium.++69+00:04:16,426 --> 00:04:18,593+Connectivity is low, and it says why.++70+00:04:18,613 --> 00:04:23,647+Everything still unknown gets a test. 119 of them.++71+00:04:24,218 --> 00:04:25,731+So this is not a finished board.++72+00:04:25,751 --> 00:04:31,262+34 connections stay open. KiCad counts 76 missing, because some seen copper++73+00:04:31,282 --> 00:04:33,105+isn't joined in the copy.++74+00:04:33,125 --> 00:04:37,466+The rails at the upper left of the bottom are largely missing, and signal++75+00:04:37,486 --> 00:04:39,139+bundles mostly read as gaps.++76+00:04:39,159 --> 00:04:43,115+And the inner copper is one way to connect it, not what's actually inside.++77+00:04:43,682 --> 00:04:48,729+Every stage is saved in the flow window. 110 recorded steps you can replay.++78+00:04:49,308 --> 00:04:54,732+From the first prompt to the report took about 6.5 hours of AI time, with idle++79+00:04:54,752 --> 00:04:56,756+gaps over 15 minutes cut out.++80+00:04:56,776 --> 00:05:05,483+914,981 output tokens, and 272 million cache reads, across 463 model calls.++81+00:05:05,503 --> 00:05:10,357+Next up: real measurements on this board, and a second board, before any of it++82+00:05:10,377 --> 00:05:11,107+goes public.+
videos/driver-re2-process.video.jsonadded+84@@ -0,0 +1,84 @@+{+ "video": "/adom/ai-flow-reverse-engineering/render/videos/driver-re2-process.mp4",+ "title": "Reverse engineering a PCB from photos: the Driver board",+ "poster": "/adom/ai-flow-reverse-engineering/render/videos/driver-re2-process-poster.jpg",+ "chapters": [+ {+ "t": 0,+ "title": "Intro"+ },+ {+ "t": 5.0,+ "title": "The request"+ },+ {+ "t": 16.1,+ "title": "A new program"+ },+ {+ "t": 33.43,+ "title": "Photos"+ },+ {+ "t": 45.23,+ "title": "Scale"+ },+ {+ "t": 60.1,+ "title": "Parts"+ },+ {+ "t": 77.03,+ "title": "Blocks"+ },+ {+ "t": 93.4,+ "title": "The miss"+ },+ {+ "t": 106.0,+ "title": "Reading the copper"+ },+ {+ "t": 127.7,+ "title": "Vias"+ },+ {+ "t": 152.8,+ "title": "The copy"+ },+ {+ "t": 162.3,+ "title": "Nets"+ },+ {+ "t": 177.47,+ "title": "The router"+ },+ {+ "t": 197.9,+ "title": "Layer count"+ },+ {+ "t": 223.43,+ "title": "Rules"+ },+ {+ "t": 245.33,+ "title": "Review and tests"+ },+ {+ "t": 263.97,+ "title": "Not done"+ },+ {+ "t": 283.43,+ "title": "The record"+ },+ {+ "t": 289.03,+ "title": "Cost"+ }+ ],+ "captions": "WEBVTT\n\n00:00:01.952 --> 00:00:05.849\nIt starts with four photos of a motor driver board, and one request.\n\n00:00:05.869 --> 00:00:10.135\nFind the parts, the functional blocks, the pours and the routing.\n\n00:00:10.155 --> 00:00:11.794\nCopy everything you can see.\n\n00:00:11.814 --> 00:00:15.780\nThen work out what you can't, pick a layer count, and say how sure you are.\n\n00:00:16.361 --> 00:00:21.041\nThe first attempt reused the existing AI Flow program, and Caleb called that\n\n00:00:21.061 --> 00:00:21.288\nout.\n\n00:00:21.308 --> 00:00:25.908\nSo this became its own Rust program, with its own copper reader and its own\n\n00:00:25.928 --> 00:00:26.339\nrouter.\n\n00:00:26.359 --> 00:00:29.894\nThe program does the measuring. The AI does the naming.\n\n00:00:29.914 --> 00:00:33.128\nEleven steps, and each one records what it produced.\n\n00:00:33.690 --> 00:00:35.968\nTwo photos of the top, two of the bottom.\n\n00:00:35.988 --> 00:00:39.805\nThe program finds the board edge in each one and straightens it.\n\n00:00:39.825 --> 00:00:44.512\nThen it turns the bottom over to line up with the top. 38 holes agree, 2\n\n00:00:44.532 --> 00:00:44.904\ndon't.\n\n00:00:45.482 --> 00:00:51.031\nScale comes from the board itself. The header rows have known pitches, 2 mm\n\n00:00:51.051 --> 00:00:51.923\nand 2.54 mm.\n\n00:00:51.943 --> 00:00:55.113\nThat gives 46.6 pixels per millimeter.\n\n00:00:55.133 --> 00:00:59.787\nThe driver chip's 6 mm body settles which pitch standard the rows are.\n\n00:01:00.360 --> 00:01:02.841\nThen the parts, 137 of them.\n\n00:01:02.861 --> 00:01:06.374\n103 are placed by their own pads on the photo.\n\n00:01:06.394 --> 00:01:12.507\nMarkings get read where they're legible, like this TI DRV8323S.\n\n00:01:12.527 --> 00:01:16.699\nWhere they aren't, the program says so. 91 parts still need a test.\n\n00:01:17.284 --> 00:01:20.918\nSilkscreen and circuit role sort them into 11 blocks.\n\n00:01:20.938 --> 00:01:26.152\nPower entry, the three-phase power stage, bridge sensing, the logic supply.\n\n00:01:26.172 --> 00:01:31.719\nThe gate driver, the microcontroller, CAN, AUX, the fan, motor temperature and\n\n00:01:31.739 --> 00:01:33.074\nthe mounting holes.\n\n00:01:33.658 --> 00:01:38.749\nThen came the real miss. The first copy had 58 pours, all on the bottom, and\n\n00:01:38.769 --> 00:01:40.026\nnot a single track.\n\n00:01:40.046 --> 00:01:44.773\nCaleb looked at it and said fill and via recognition was completely lacking.\n\n00:01:44.793 --> 00:01:45.676\nThat was correct.\n\n00:01:46.249 --> 00:01:50.301\nSo the reader was rewritten. Under solder mask, copper looks a little lighter\n\n00:01:50.321 --> 00:01:53.209\nthan bare laminate, compared with its own neighborhood.\n\n00:01:53.229 --> 00:01:56.060\nThin dark lines mark the gaps between copper.\n\n00:01:56.080 --> 00:02:02.294\nFollow those gaps and the board falls apart into islands. 1,444 of them.\n\n00:02:02.314 --> 00:02:07.370\nThat became 116 pours and 314 tracks, on both faces.\n\n00:02:07.949 --> 00:02:13.882\nVias are next. 2,681 candidates, and 1,028 kept.\n\n00:02:13.902 --> 00:02:18.031\nThey're tented on the top, so only 45 show on both faces.\n\n00:02:18.051 --> 00:02:22.994\nZoom in and the misses show. Up to a third land on something pale, mostly\n\n00:02:23.014 --> 00:02:24.965\nsilkscreen letters and lines.\n\n00:02:24.985 --> 00:02:29.825\nAnd the 3 read as leading only inward look like ordinary domes in a stitching\n\n00:02:29.845 --> 00:02:32.477\nfield. So that's no proof of inner layers.\n\n00:02:33.050 --> 00:02:37.964\nAll of that goes straight into a KiCad board, as photographed, before anything\n\n00:02:37.984 --> 00:02:38.659\nis guessed.\n\n00:02:38.679 --> 00:02:41.979\nHere's the copy laid over the top photo, and over the bottom.\n\n00:02:42.550 --> 00:02:48.074\nNow for what nobody can see. Datasheets and the circuit fill in the rest of\n\n00:02:48.094 --> 00:02:51.252\nthe nets. 77 nets, 249 connections to make.\n\n00:02:51.272 --> 00:02:56.221\n99 pins disagree with the copper they seem to touch. Those get reported, not\n\n00:02:56.241 --> 00:02:57.136\nquietly fixed.\n\n00:02:57.726 --> 00:03:02.040\nThen the router. It's written for this job, and it uses every inner layer.\n\n00:03:02.060 --> 00:03:06.974\nWhen photographed pours were hard walls, 235 connections stayed open.\n\n00:03:06.994 --> 00:03:11.990\nReal vias pass through pours, so seen copper became expensive to cross instead\n\n00:03:12.010 --> 00:03:12.826\nof forbidden.\n\n00:03:12.846 --> 00:03:17.587\n17 recorded runs later, 6 and 8 layers are down to about 30.\n\n00:03:18.157 --> 00:03:21.244\nThe layer count comes from how hard that is.\n\n00:03:21.264 --> 00:03:27.699\n4 layers: 54 open, and 327 mm cut through copper the photos show.\n\n00:03:27.719 --> 00:03:30.646\n6 layers: 34 open, 24 mm.\n\n00:03:30.666 --> 00:03:37.037\n8 layers: 29 open, 30 mm. That's no real gain, since runs vary by about a\n\n00:03:37.057 --> 00:03:37.737\nquarter.\n\n00:03:37.757 --> 00:03:42.411\nSo the proposal is 6. It's a measure of difficulty. Nobody has seen inside\n\n00:03:42.431 --> 00:03:43.105\nthis board.\n\n00:03:43.693 --> 00:03:48.776\nThe rules were set from the start: KiCad's defaults, 0.2 mm track and\n\n00:03:48.796 --> 00:03:49.516\nclearance.\n\n00:03:49.536 --> 00:03:53.723\nMost of what's left open is fan-out at the two QFN chips.\n\n00:03:53.743 --> 00:04:00.570\nThe same copy at JLC-style rules, 0.127 mm, leaves just 2 open at 6 layers.\n\n00:04:00.590 --> 00:04:05.024\nSo that's mostly a rules limit. That run has no valid design rule check yet.\n\n00:04:05.592 --> 00:04:10.631\nThen it reviews itself, in a loop. 4 passes, and the last one changes nothing.\n\n00:04:10.651 --> 00:04:15.930\nBlocks and placement come out high. Identity, values, copper, vias and layers,\n\n00:04:15.950 --> 00:04:16.406\nmedium.\n\n00:04:16.426 --> 00:04:18.593\nConnectivity is low, and it says why.\n\n00:04:18.613 --> 00:04:23.647\nEverything still unknown gets a test. 119 of them.\n\n00:04:24.218 --> 00:04:25.731\nSo this is not a finished board.\n\n00:04:25.751 --> 00:04:31.262\n34 connections stay open. KiCad counts 76 missing, because some seen copper\n\n00:04:31.282 --> 00:04:33.105\nisn't joined in the copy.\n\n00:04:33.125 --> 00:04:37.466\nThe rails at the upper left of the bottom are largely missing, and signal\n\n00:04:37.486 --> 00:04:39.139\nbundles mostly read as gaps.\n\n00:04:39.159 --> 00:04:43.115\nAnd the inner copper is one way to connect it, not what's actually inside.\n\n00:04:43.682 --> 00:04:48.729\nEvery stage is saved in the flow window. 110 recorded steps you can replay.\n\n00:04:49.308 --> 00:04:54.732\nFrom the first prompt to the report took about 6.5 hours of AI time, with idle\n\n00:04:54.752 --> 00:04:56.756\ngaps over 15 minutes cut out.\n\n00:04:56.776 --> 00:05:05.483\n914,981 output tokens, and 272 million cache reads, across 463 model calls.\n\n00:05:05.503 --> 00:05:10.357\nNext up: real measurements on this board, and a second board, before any of it\n\n00:05:10.377 --> 00:05:11.107\ngoes public.\n\n"+}
videos/driver-re2-process.vttadded+248@@ -0,0 +1,248 @@+WEBVTT++00:00:01.952 --> 00:00:05.849+It starts with four photos of a motor driver board, and one request.++00:00:05.869 --> 00:00:10.135+Find the parts, the functional blocks, the pours and the routing.++00:00:10.155 --> 00:00:11.794+Copy everything you can see.++00:00:11.814 --> 00:00:15.780+Then work out what you can't, pick a layer count, and say how sure you are.++00:00:16.361 --> 00:00:21.041+The first attempt reused the existing AI Flow program, and Caleb called that++00:00:21.061 --> 00:00:21.288+out.++00:00:21.308 --> 00:00:25.908+So this became its own Rust program, with its own copper reader and its own++00:00:25.928 --> 00:00:26.339+router.++00:00:26.359 --> 00:00:29.894+The program does the measuring. The AI does the naming.++00:00:29.914 --> 00:00:33.128+Eleven steps, and each one records what it produced.++00:00:33.690 --> 00:00:35.968+Two photos of the top, two of the bottom.++00:00:35.988 --> 00:00:39.805+The program finds the board edge in each one and straightens it.++00:00:39.825 --> 00:00:44.512+Then it turns the bottom over to line up with the top. 38 holes agree, 2++00:00:44.532 --> 00:00:44.904+don't.++00:00:45.482 --> 00:00:51.031+Scale comes from the board itself. The header rows have known pitches, 2 mm++00:00:51.051 --> 00:00:51.923+and 2.54 mm.++00:00:51.943 --> 00:00:55.113+That gives 46.6 pixels per millimeter.++00:00:55.133 --> 00:00:59.787+The driver chip's 6 mm body settles which pitch standard the rows are.++00:01:00.360 --> 00:01:02.841+Then the parts, 137 of them.++00:01:02.861 --> 00:01:06.374+103 are placed by their own pads on the photo.++00:01:06.394 --> 00:01:12.507+Markings get read where they're legible, like this TI DRV8323S.++00:01:12.527 --> 00:01:16.699+Where they aren't, the program says so. 91 parts still need a test.++00:01:17.284 --> 00:01:20.918+Silkscreen and circuit role sort them into 11 blocks.++00:01:20.938 --> 00:01:26.152+Power entry, the three-phase power stage, bridge sensing, the logic supply.++00:01:26.172 --> 00:01:31.719+The gate driver, the microcontroller, CAN, AUX, the fan, motor temperature and++00:01:31.739 --> 00:01:33.074+the mounting holes.++00:01:33.658 --> 00:01:38.749+Then came the real miss. The first copy had 58 pours, all on the bottom, and++00:01:38.769 --> 00:01:40.026+not a single track.++00:01:40.046 --> 00:01:44.773+Caleb looked at it and said fill and via recognition was completely lacking.++00:01:44.793 --> 00:01:45.676+That was correct.++00:01:46.249 --> 00:01:50.301+So the reader was rewritten. Under solder mask, copper looks a little lighter++00:01:50.321 --> 00:01:53.209+than bare laminate, compared with its own neighborhood.++00:01:53.229 --> 00:01:56.060+Thin dark lines mark the gaps between copper.++00:01:56.080 --> 00:02:02.294+Follow those gaps and the board falls apart into islands. 1,444 of them.++00:02:02.314 --> 00:02:07.370+That became 116 pours and 314 tracks, on both faces.++00:02:07.949 --> 00:02:13.882+Vias are next. 2,681 candidates, and 1,028 kept.++00:02:13.902 --> 00:02:18.031+They're tented on the top, so only 45 show on both faces.++00:02:18.051 --> 00:02:22.994+Zoom in and the misses show. Up to a third land on something pale, mostly++00:02:23.014 --> 00:02:24.965+silkscreen letters and lines.++00:02:24.985 --> 00:02:29.825+And the 3 read as leading only inward look like ordinary domes in a stitching++00:02:29.845 --> 00:02:32.477+field. So that's no proof of inner layers.++00:02:33.050 --> 00:02:37.964+All of that goes straight into a KiCad board, as photographed, before anything++00:02:37.984 --> 00:02:38.659+is guessed.++00:02:38.679 --> 00:02:41.979+Here's the copy laid over the top photo, and over the bottom.++00:02:42.550 --> 00:02:48.074+Now for what nobody can see. Datasheets and the circuit fill in the rest of++00:02:48.094 --> 00:02:51.252+the nets. 77 nets, 249 connections to make.++00:02:51.272 --> 00:02:56.221+99 pins disagree with the copper they seem to touch. Those get reported, not++00:02:56.241 --> 00:02:57.136+quietly fixed.++00:02:57.726 --> 00:03:02.040+Then the router. It's written for this job, and it uses every inner layer.++00:03:02.060 --> 00:03:06.974+When photographed pours were hard walls, 235 connections stayed open.++00:03:06.994 --> 00:03:11.990+Real vias pass through pours, so seen copper became expensive to cross instead++00:03:12.010 --> 00:03:12.826+of forbidden.++00:03:12.846 --> 00:03:17.587+17 recorded runs later, 6 and 8 layers are down to about 30.++00:03:18.157 --> 00:03:21.244+The layer count comes from how hard that is.++00:03:21.264 --> 00:03:27.699+4 layers: 54 open, and 327 mm cut through copper the photos show.++00:03:27.719 --> 00:03:30.646+6 layers: 34 open, 24 mm.++00:03:30.666 --> 00:03:37.037+8 layers: 29 open, 30 mm. That's no real gain, since runs vary by about a++00:03:37.057 --> 00:03:37.737+quarter.++00:03:37.757 --> 00:03:42.411+So the proposal is 6. It's a measure of difficulty. Nobody has seen inside++00:03:42.431 --> 00:03:43.105+this board.++00:03:43.693 --> 00:03:48.776+The rules were set from the start: KiCad's defaults, 0.2 mm track and++00:03:48.796 --> 00:03:49.516+clearance.++00:03:49.536 --> 00:03:53.723+Most of what's left open is fan-out at the two QFN chips.++00:03:53.743 --> 00:04:00.570+The same copy at JLC-style rules, 0.127 mm, leaves just 2 open at 6 layers.++00:04:00.590 --> 00:04:05.024+So that's mostly a rules limit. That run has no valid design rule check yet.++00:04:05.592 --> 00:04:10.631+Then it reviews itself, in a loop. 4 passes, and the last one changes nothing.++00:04:10.651 --> 00:04:15.930+Blocks and placement come out high. Identity, values, copper, vias and layers,++00:04:15.950 --> 00:04:16.406+medium.++00:04:16.426 --> 00:04:18.593+Connectivity is low, and it says why.++00:04:18.613 --> 00:04:23.647+Everything still unknown gets a test. 119 of them.++00:04:24.218 --> 00:04:25.731+So this is not a finished board.++00:04:25.751 --> 00:04:31.262+34 connections stay open. KiCad counts 76 missing, because some seen copper++00:04:31.282 --> 00:04:33.105+isn't joined in the copy.++00:04:33.125 --> 00:04:37.466+The rails at the upper left of the bottom are largely missing, and signal++00:04:37.486 --> 00:04:39.139+bundles mostly read as gaps.++00:04:39.159 --> 00:04:43.115+And the inner copper is one way to connect it, not what's actually inside.++00:04:43.682 --> 00:04:48.729+Every stage is saved in the flow window. 110 recorded steps you can replay.++00:04:49.308 --> 00:04:54.732+From the first prompt to the report took about 6.5 hours of AI time, with idle++00:04:54.752 --> 00:04:56.756+gaps over 15 minutes cut out.++00:04:56.776 --> 00:05:05.483+914,981 output tokens, and 272 million cache reads, across 463 model calls.++00:05:05.503 --> 00:05:10.357+Next up: real measurements on this board, and a second board, before any of it++00:05:10.377 --> 00:05:11.107+goes public.+