component
ADUM3160WBRWZ
Public Made by Adomby adom
Analog Devices Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"number": "1",
"name": "VBUS1",
"type": "power_in",
"description": "Side 1 power supply: connect to the USB bus when operating from 4.5 V to 5.5 V, or connect to VDD1 and a 3.3 V supply when operating from 3.3 V, with a bypass capacitor to GND1 required."
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{
"number": "2",
"name": "GND1",
"type": "power_in",
"description": "Ground reference for Side 1; internally connected to Pin 8, and both pins should be connected to a common ground."
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{
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"type": "power_in",
"description": "Side 1 3.3 V supply/LDO output used for bypass capacitor to GND1 (required) and as the tie point for pull-up signals such as PDEN and SPU."
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{
"number": "4",
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{
"number": "5",
"name": "SPU",
"type": "input",
"description": "Upstream buffer speed select, active high: high selects full speed slew rate, timing and logic conventions, low selects low speed; must be set via VDD1 or GND1 and match Pin 13."
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{
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{
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"description": "Upstream pull-up enable: can be tied to VDD2 for enumeration at power-up, or driven by an external control signal to delay enumeration."
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"number": "13",
"name": "SPD",
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"description": "Downstream buffer speed select, active high: high selects full speed, low selects low speed; must be set via VDD2 or GND2 and match Pin 5."
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{
"number": "14",
"name": "VDD2",
"type": "power_in",
"description": "Side 2 3.3 V supply/LDO output used for bypass capacitor to GND2 (required) and as the tie point for pull-up signals such as SPD."
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{
"number": "15",
"name": "GND2",
"type": "power_in",
"description": "Ground reference for Side 2; internally connected to Pin 9, and both pins should be connected to a common ground."
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{
"number": "16",
"name": "VBUS2",
"type": "power_in",
"description": "Side 2 power supply: connect to the USB bus when operating from 4.5 V to 5.5 V, or connect to VDD2 and a 3.3 V supply when operating from 3.3 V, with a bypass capacitor to GND2 required."
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{
"name": "Single-Ended Logic High Input Threshold",
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{
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{
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"typ": null,
"max": 325,
"conditions": "CL = 50 pF, SPD = SPU = low, VDD1, VDD2 = 3.3 V",
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{
"name": "Side 1 Output Rise/Fall Time, Low Speed (10% to 90%)",
"symbol": "tRL, tFL",
"kind": "timing",
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"min": 75,
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"conditions": "CL = 450 pF, SPD = SPU = low, VDD1, VDD2 = 3.3 V",
"source_page": 3,
"source": "datasheet"
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{
"name": "Low Speed Differential Jitter, Next Transition",
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{
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