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ADUM3160WBRWZ
Public Made by Adomby adom
Analog Devices Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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ADUM3160WBRWZ
Analog Devices · Digital Isolators · SOIC-16-300mil
ADUM3160WBRWZ from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBUS1 | power_in | Side 1 power supply: connect to the USB bus when operating from 4.5 V to 5.5 V, or connect to VDD1 and a 3.3 V supply when operating from 3.3 V, with a bypass capacitor to GND1 required. |
| 2 | GND1 | power_in | Ground reference for Side 1; internally connected to Pin 8, and both pins should be connected to a common ground. |
| 3 | VDD1 | power_in | Side 1 3.3 V supply/LDO output used for bypass capacitor to GND1 (required) and as the tie point for pull-up signals such as PDEN and SPU. |
| 4 | PDEN | input | Pull-down enable, read when exiting reset; must be connected to VDD1 for standard operation, and connecting it to GND1 disconnects the downstream pull-down resistors to allow buffer impedance measurements. |
| 5 | SPU | input | Upstream buffer speed select, active high: high selects full speed slew rate, timing and logic conventions, low selects low speed; must be set via VDD1 or GND1 and match Pin 13. |
| 6 | UD− | bidirectional | Upstream D− USB data line (input/output) on the host or cable side of the isolator. |
| 7 | UD+ | bidirectional | Upstream D+ USB data line (input/output) on the host or cable side of the isolator. |
| 8 | GND1 | power_in | Ground reference for Side 1; internally connected to Pin 2, and both pins should be connected to a common ground. |
| 9 | GND2 | power_in | Ground reference for Side 2; internally connected to Pin 15, and both pins should be connected to a common ground. |
| 10 | DD+ | bidirectional | Downstream D+ USB data line (input/output) on the peripheral controller side of the isolator. |
| 11 | DD− | bidirectional | Downstream D− USB data line (input/output) on the peripheral controller side of the isolator. |
| 12 | PIN | input | Upstream pull-up enable: can be tied to VDD2 for enumeration at power-up, or driven by an external control signal to delay enumeration. |
| 13 | SPD | input | Downstream buffer speed select, active high: high selects full speed, low selects low speed; must be set via VDD2 or GND2 and match Pin 5. |
| 14 | VDD2 | power_in | Side 2 3.3 V supply/LDO output used for bypass capacitor to GND2 (required) and as the tie point for pull-up signals such as SPD. |
| 15 | GND2 | power_in | Ground reference for Side 2; internally connected to Pin 9, and both pins should be connected to a common ground. |
| 16 | VBUS2 | power_in | Side 2 power supply: connect to the USB bus when operating from 4.5 V to 5.5 V, or connect to VDD2 and a 3.3 V supply when operating from 3.3 V, with a bypass capacitor to GND2 required. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-16-300mil |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD1 or VBUS1 Supply Current (1.5 Mbps) | IDD1 (L) | 5 | 7 | mA | 1.5 Mbps 750 kHz logic signal rate, CL = 450 pF | 3 | |
| VDD2 or VBUS2 Supply Current (1.5 Mbps) | IDD2 (L) | 5 | 7 | mA | 1.5 Mbps 750 kHz logic signal rate, CL = 450 pF | 3 | |
| VDD1 or VBUS1 Supply Current (12 Mbps) | IDD1 (F) | 6 | 8 | mA | 12 Mbps 6 MHz logic signal rate, CL = 50 pF | 3 | |
| VDD2 or VBUS2 Supply Current (12 Mbps) | IDD2 (F) | 6 | 8 | mA | 12 Mbps 6 MHz logic signal rate, CL = 50 pF | 3 | |
| VDD1 or VBUS1 Idle Current | IDD1 (I) | 1.7 | 2.3 | mA | 3 | ||
| Input Currents | IDD−, IDD+, IUD+, IUD−, ISPD, IPIN, ISPU, IPDEN | -1 | 0.1 | 1 | µA | 0 V ≤ VDD−, VDD+, VUD+, VUD−, VSPD, VPIN, VSPU, VPDEN ≤ 3.0 V | 3 |
| Single-Ended Logic High Input Threshold | VIH | 2 | V | 3 | |||
| Single-Ended Logic Low Input Threshold | VIL | 0.8 | V | 3 | |||
| Single-Ended Input Hysteresis | VHST | 0.4 | V | 3 | |||
| Differential Input Sensitivity | VDI | 0.2 | V | /VXD+ − VXD−/ | 3 | ||
| Logic High Output Voltages | VOH | 2.8 | 3.6 | V | RL = 15 kΩ, VL = 0 V | 3 | |
| Logic Low Output Voltages | VOL | 0 | 0.3 | V | RL = 1.5 kΩ, VL = 3.6 V | 3 | |
| VDD1 and VDD2 Supply Undervoltage Lockout | VUVLO | 2.4 | 3.1 | V | 3 | ||
| VBUS1 Supply Undervoltage Lockout | VUVLOB1 | 3.5 | 4.35 | V | 3 | ||
| VBUS2 Supply Undervoltage Lockout | VUVLOB2 | 3.5 | 4.4 | V | 3 | ||
| Transceiver Capacitance | CIN | 10 | pF | UD+, UD−, DD+, DD− to ground | 3 | ||
| Capacitance Matching | 10 | % | 3 | ||||
| Full Speed Driver Impedance | ZOUTH | 4 | 20 | Ω | 3 | ||
| Impedance Matching | 10 | % | 3 | ||||
| Low Speed Data Rate | 1.5 | Mbps | CL = 50 pF | 3 | |||
| Low Speed Propagation Delay | tPHL, tPLH | 325 | ns | CL = 50 pF, SPD = SPU = low, VDD1, VDD2 = 3.3 V | 3 | ||
| Side 1 Output Rise/Fall Time, Low Speed (10% to 90%) | tRL, tFL | 75 | 300 | ns | CL = 450 pF, SPD = SPU = low, VDD1, VDD2 = 3.3 V | 3 | |
| Low Speed Differential Jitter, Next Transition | /tLJN/ | 45 | ns | CL = 50 pF | 3 | ||
| Low Speed Differential Jitter, Paired Transition | /tLJP/ | 15 | ns | CL = 50 pF | 3 | ||
| Maximum Data Rate (Full Speed) | 12 | Mbps | CL = 50 pF | 3 | |||
| Full Speed Propagation Delay | tPHL, tPLH | 20 | 60 | 70 | ns | CL = 50 pF, SPD = SPU = high, VDD1, VDD2 = 3.3 V | 3 |
| Full Speed Output Rise/Fall Time (10% to 90%) | tRF, tFF | 4 | 20 | ns | CL = 50 pF, SPD = SPU = high, VDD1, VDD2 = 3.3 V | 3 | |
| Full Speed Differential Jitter, Next Transition | /tHJN/ | 3 | ns | CL = 50 pF | 3 | ||
| Full Speed Differential Jitter, Paired Transition | /tHJP/ | 1 | ns | CL = 50 pF | 3 | ||
| Common-Mode Transient Immunity at Logic High Output | /CMH/ | 25 | 35 | kV/µs | VUD+, VUD−, VDD+, VDD− = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V | 4 | |
| Common-Mode Transient Immunity at Logic Low Output | /CML/ | 25 | 35 | kV/µs | VUD+, VUD−, VDD+, VDD− = 0 V, VCM = 1000 V, transient magnitude = 800 V | 4 | |
| Capacitance (Input to Output) | CI-O | 2.2 | pF | f = 1 MHz | 4 | ||
| Input Capacitance | CI | 4 | pF | Input capacitance is from any input data pin to ground | 4 | ||
| IC Junction-to-Ambient Thermal Resistance | θJA | 45 | °C/W | Thermocouple located at center of package underside | 4 | ||
| Operating Temperature | TA | -40 | 105 | °C | 7 | ||
| Supply Voltages | VBUS1, VBUS2 | 3 | 5.5 | V | 7 | ||
| Input Signal Rise and Fall Times | 1 | ms | 7 | ||||
| Storage Temperature | TST | -40 | 150 | °C | 8 | ||
| Ambient Operating Temperature | TA | -40 | 105 | °C | 8 | ||
| Supply Voltages | VBUS1, VBUS2, VDD1, VDD2 | -0.5 | 6.5 | V | Relative to respective grounds | 8 | |
| Input Voltage | VUD+, VUD−, VSPU | -0.5 | V | Upper limit printed as VDD1 + 0.5 V | 8 | ||
| Output Voltage | VDD−, VDD+, VSPD, VPIN | -0.5 | V | Upper limit printed as VDD2 + 0.5 V | 8 | ||
| Average Output Current per Pin, Side 1 | IO1 | -10 | 10 | mA | 8 | ||
| Average Output Current per Pin, Side 2 | IO2 | -10 | 10 | mA | 8 | ||
| Common-Mode Transients | -100 | 100 | kV/µs | Across the insulation barrier | 8 | ||
| Maximum Continuous Working Voltage, AC Bipolar Waveform | 645 | VPEAK | Reinforced insulation rating per IEC 60747-17 (VDE 0884-17) | 8 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM3160 is proof tested by applying an insulation test voltage ≥ 1208 VPEAK for 1 sec (partial discharge detection limit = 5 pC). The asteri | 5 |
CAD (KiCad official)
- Symbol:
ADUM3160WBRWZ - Footprint:
Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
adum3160wbrwz-etched.step/adum3160wbrwz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adum3160wbrwz.step/adum3160wbrwz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (15 pp, sha256
339238edd188daff, retrieved 2026-11-11, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).