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ADUM1402ARWZ-RL

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Analog Devices Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADUM1402ARWZ-RL

Analog Devices · Digital Isolators · SOIC-16-300mil

ADUM1402ARWZ-RL from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1.
2 GND1 power_in Ground 1, the ground reference for isolator side 1; internally connected to pin 8, and connecting both to GND1 is recommended.
3 VIA input Logic input A on isolator side 1.
4 VIB input Logic input B on isolator side 1.
5 VOC output Logic output C, enabled when VE1 is high or disconnected and disabled when VE1 is low.
6 VOD output Logic output D, enabled when VE1 is high or disconnected and disabled when VE1 is low.
7 VE1 input Output enable 1, active high logic input for VOC and VOD; connecting it to an external logic high or low is recommended in noisy environments.
8 GND1 power_in Ground 1, the ground reference for isolator side 1; internally connected to pin 2, and connecting both to GND1 is recommended.
9 GND2 power_in Ground 2, the ground reference for isolator side 2; internally connected to pin 15, and connecting both to GND2 is recommended.
10 VE2 input Output enable 2, active high logic input for VOA and VOB; VOA and VOB are enabled when VE2 is high or disconnected and disabled when low, and connecting it to an external logic high or low is recommended in noisy environments.
11 VID input Logic input D on isolator side 2.
12 VIC input Logic input C on isolator side 2.
13 VOB output Logic output B on isolator side 2, enabled when VE2 is high or disconnected and disabled when VE2 is low.
14 VOA output Logic output A on isolator side 2, enabled when VE2 is high or disconnected and disabled when VE2 is low.
15 GND2 power_in Ground 2, the ground reference for isolator side 2; internally connected to pin 9, and connecting both to GND2 is recommended.
16 VDD2 power_in Supply voltage for isolator side 2.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature (TA), commercial grade TA -40 105 °C Footnote 1: does not apply to W automotive grades 20
Supply Voltages (VDD1, VDD2) VDD1, VDD2 2.7 5.5 V Footnotes 1, 3: relative to respective ground 20
Input Signal Rise and Fall Times 1 ms 20
Storage Temperature TST -65 150 °C 21
Ambient Operating Temperature TA -40 105 °C Footnote 1: does not apply to W automotive grades 21
Supply Voltages (VDD1, VDD2) VDD1, VDD2 -0.5 7 V 21
Input Voltage (VIA, VIB, VIC, VID, VE1, VE2) VIA, VIB, VIC, VID, VE1, VE2 -0.5 V Maximum printed as VDDI + 0.5 V 21
Output Voltage (VOA, VOB, VOC, VOD) VOA, VOB, VOC, VOD -0.5 V Maximum printed as VDDO + 0.5 V 21
Average Output Current per Pin, Side 1 IO1 -18 18 mA 21
Average Output Current per Pin, Side 2 IO2 -22 22 mA 21
Common-Mode Transients -100 100 kV/µs Across the insulation barrier 21
Input Supply Current per Channel, Quiescent (5 V) IDDI (Q) 0.5 0.53 mA 4
Output Supply Current per Channel, Quiescent (5 V) IDDO (Q) 0.19 0.21 mA 4
ADuM1402 VDD1 or VDD2 Supply Current (5 V) IDD1 (Q), IDD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq. 4
Input Currents (5 V, all models) IIA, IIB, IIC, IID, IE1, IE2 -10 0.01 10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 4
Logic High Input Threshold (5 V) VIH, VEH 2 V 4
Logic Low Input Threshold (5 V) VIL, VEL 0.8 V 4
Logic High Output Voltage, 20 µA (5 V) VOAH, VOBH, VOCH, VODH 5 V IOx = −20 µA, VIx = VIxH; printed min is (VDD1 or VDD2) − 0.1 V 4
Logic High Output Voltage, 4 mA (5 V) VOAH, VOBH, VOCH, VODH 4.8 V IOx = −4 mA, VIx = VIxH; printed min is (VDD1 or VDD2) − 0.4 V 4
Logic Low Output Voltage, 20 µA (5 V/3 V, all models) VOAL, VOBL, VOCL, VODL 0 0.1 V IOx = 20 µA, VIx = VIxL 4
Logic Low Output Voltage, 400 µA (all models) VOAL, VOBL, VOCL, VODL 0.04 0.1 V IOx = 400 µA, VIx = VIxL 4
Logic Low Output Voltage, 4 mA (all models) VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 4
Minimum Pulse Width, ARW (5 V) PW 1000 ns CL = 15 pF, CMOS signal levels 4
Maximum Data Rate, ARW (5 V) 1 Mbps CL = 15 pF, CMOS signal levels 4
Propagation Delay, ARW (5 V) tPHL, tPLH 50 65 100 ns CL = 15 pF, CMOS signal levels 4
Pulse Width Distortion, /tPLH − tPHL/, ARW (5 V) PWD 40 ns CL = 15 pF, CMOS signal levels 5
Change vs. Temperature, ARW (5 V) 11 ps/°C CL = 15 pF, CMOS signal levels 5
Propagation Delay Skew, ARW (5 V) tPSK 50 ns CL = 15 pF, CMOS signal levels 5
Channel-to-Channel Matching, ARW (5 V) tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels 5
Output Disable Propagation Delay (High/Low to High Impedance) tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels 5
Output Enable Propagation Delay (High Impedance to High/Low) tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels 5
Output Rise/Fall Time (10% to 90%), 5 V tR/tF 2.5 ns CL = 15 pF, CMOS signal levels 5
Common-Mode Transient Immunity at Logic High Output /CMH/ 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V 5
Common-Mode Transient Immunity at Logic Low Output /CML/ 25 35 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V 5
Input Supply Current per Channel, Quiescent (3 V) IDDI (Q) 0.26 0.31 mA 6
Output Supply Current per Channel, Quiescent (3 V) IDDO (Q) 0.11 0.14 mA 6
ADuM1402 VDD1 or VDD2 Supply Current (3 V) IDD1 (Q), IDD2 (Q) 0.9 1.5 mA DC to 1 MHz logic signal freq. 6
Logic High Input Threshold (3 V) VIH, VEH 1.6 V 6
Logic Low Input Threshold (3 V) VIL, VEL 0.4 V 6
Logic High Output Voltage, 20 µA (3 V) VOAH, VOBH, VOCH, VODH 3 V IOx = −20 µA, VIx = VIxH; printed min is (VDD1 or VDD2) − 0.1 V 6
Logic High Output Voltage, 4 mA (3 V) VOAH, VOBH, VOCH, VODH 2.8 V IOx = −4 mA, VIx = VIxH; printed min is (VDD1 or VDD2) − 0.4 V 6
Propagation Delay, ARW (3 V) tPHL, tPLH 50 75 100 ns CL = 15 pF, CMOS signal levels 6
Output Rise/Fall Time (10% to 90%), 3 V tR/tF 3 ns CL = 15 pF, CMOS signal levels 7
Input Supply Current per Channel, Quiescent (5 V/3 V operation) IDDI (Q) 0.5 0.53 mA 8
Input Supply Current per Channel, Quiescent (3 V/5 V operation) IDDI (Q) 0.26 0.31 mA 8
Output Supply Current per Channel, Quiescent (5 V/3 V operation) IDDO (Q) 0.11 0.14 mA 8
Output Supply Current per Channel, Quiescent (3 V/5 V operation) IDDO (Q) 0.19 0.21 mA 8
ADuM1402 VDD1 Supply Current, DC to 2 Mbps (5 V/3 V operation) IDD1 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq. 9
ADuM1402 VDD1 Supply Current, DC to 2 Mbps (3 V/5 V operation) IDD1 (Q) 0.9 1.5 mA DC to 1 MHz logic signal freq. 9
ADuM1402 VDD2 Supply Current, DC to 2 Mbps (5 V/3 V operation) IDD2 (Q) 0.9 1.5 mA DC to 1 MHz logic signal freq. 9
ADuM1402 VDD2 Supply Current, DC to 2 Mbps (3 V/5 V operation) IDD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq. 9
Logic High Input Threshold (5 V/3 V operation) VIH, VEH 2 V 9
Logic High Input Threshold (3 V/5 V operation) VIH, VEH 1.6 V 9
Logic Low Input Threshold (5 V/3 V operation) VIL, VEL 0.8 V 9
Logic Low Input Threshold (3 V/5 V operation) VIL, VEL 0.4 V 9
Propagation Delay, ARW (mixed 5 V/3 V or 3 V/5 V) tPHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels 9
Output Rise/Fall Time (10% to 90%) (5 V/3 V operation) tR/tF 3 ns CL = 15 pF, CMOS signal levels 10
Output Rise/Fall Time (10% to 90%) (3 V/5 V operation) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels 10
IC Junction-to-Case Thermal Resistance, Side 1 θJCI 33 °C/W Thermocouple located at center of package underside 19
IC Junction-to-Case Thermal Resistance, Side 2 θJCO 28 °C/W Thermocouple located at center of package underside 19

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC given channel, respectively. See the PC Board Layout section. 5 See Figure 4 for maximum rated current values for various temperatures. 6 This refers to common-mode transients across the insulation ba 21

CAD (KiCad official)

  • Symbol: ADUM1402ARWZ-RL
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: adum1402arwz-rl-etched.step / adum1402arwz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum1402arwz-rl.step / adum1402arwz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 1f063e92f3a10974, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF