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ADS8568SRGCR
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Texas Instruments Analog To Digital Converters (ADCs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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ADS8568SRGCR
Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-64-EP(9x9)
ADS8568SRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | HVSS | power_in | Negative supply voltage for the analog inputs, specified from -16.5 V to -5.0 V with -15.0 V nominal. |
| 2 | CH_D1 | passive | Analog input of channel D1; input range is set by the RANGE pin or CONFIG bit C19 and the channel can be powered down with CONFIG bit C18. |
| 3 | REFDN | passive | Decoupling capacitor input for the channel pair D reference, to be connected to the decoupling capacitor and AGND. |
| 4 | AVDD | power_in | Analog power supply, specified from 4.5 V to 5.5 V with 5.0 V nominal. |
| 5 | AGND | power_in | Analog ground; connect to the analog ground plane. |
| 6 | REFDP | passive | Decoupling capacitor input for the channel pair D reference, to be connected to the decoupling capacitor. |
| 7 | CH_D0 | passive | Analog input of channel D0; input range is set by the RANGE pin or CONFIG bit C19 and the channel can be powered down with CONFIG bit C18. |
| 8 | PAR/SER | input | Interface mode selection input; low selects the parallel interface and high enables the serial interface. |
| 9 | STBY | input | In hardware mode, low powers down the entire device including clock source and reference; in software mode, connect to DGND or DVDD. |
| 10 | RESET | input | Active-high reset input that aborts conversions and resets CONFIG to 000003FFh; a valid reset pulse must be at least 50 ns long. |
| 11 | REFEN/WR | input | In hardware mode, high enables the internal reference and low applies an external reference at REFIO; in software mode it is the write input. |
| 12 | RD | input | Read data input; when low the parallel data output is enabled if CS is low, and it must be connected to DGND. |
| 13 | CS/FS | input | Chip-select input enables the parallel interface when low; in serial mode it is the frame synchronization input, where the FS falling edge controls the frame transfer. |
| 14 | AVDD | power_in | Analog power supply, specified from 4.5 V to 5.5 V with 5.0 V nominal. |
| 15 | AGND | power_in | Analog ground; connect to the analog ground plane. |
| 16 | DB15/SDO_D | bidirectional | Data bit 15 (MSB) input/output; it is the SDO_D data output when SEL_CD = 1 and must be tied to DGND when SEL_CD = 0. |
| 17 | DB14/SDO_C | bidirectional | Data bit 14 input/output; it is the SDO_C data output when SEL_CD = 1 and must be tied to DGND when SEL_CD = 0. |
| 18 | DB13/SDO_B | bidirectional | Data bit 13 input/output; it is the SDO_B data output when SEL_B = 1 and must be tied to DGND when SEL_B = 0. |
| 19 | DB12/SDO_A | bidirectional | Data bit 12 input/output; it is the data output for channel pair A. |
| 20 | DB11/REFBUFEN | bidirectional | Data bit 11 input/output; in hardware mode low enables all internal reference buffers (mandatory if the internal reference is used) and high disables them. |
| 21 | DB10/SCLK | bidirectional | Data bit 10 input/output; serves as the serial interface clock input. |
| 22 | DB9/SDI | bidirectional | Data bit 9 input/output; connect to DGND in hardware mode and serves as the serial data input in software mode. |
| 23 | DB8/DCEN | bidirectional | Data bit 8 input/output; daisy-chain enable input, connected to DGND if daisy-chain mode is not used. |
| 24 | DGND | power_in | Buffer I/O ground; connect to the digital ground plane. |
| 25 | DVDD | power_in | Buffer I/O supply, specified from 2.7 V to 5.5 V with 3.3 V nominal. |
| 26 | DB7 | bidirectional | Data bit 7 input/output; must be connected to DGND. |
| 27 | DB6/SEL_B | bidirectional | Data bit 6 input/output; when low SDO_B is disabled and all eight channels are available only through SDO_A. |
| 28 | DB5/SEL_CD | bidirectional | Data bit 5 input/output; selects SDO_C and SDO_D, with high placing channel pairs C and D on SDO_C and SDO_D. |
| 29 | DB4 | bidirectional | Data bit 4 input/output; connect to DGND. |
| 30 | DB3/DCIN_A | bidirectional | Data bit 3 input/output; when DCEN = 1 it is the daisy-chain data input for SDO_A of the previous device, and when DCEN = 0 it is connected to DGND. |
| 31 | DB2/DCIN_B | bidirectional | Data bit 2 input/output; when DCEN = 1 and SEL_B = 1 it is the daisy-chain data input for SDO_B, and when DCEN = 0 it is connected to DGND. |
| 32 | DB1/DCIN_C | bidirectional | Data bit 1 input/output; when DCEN = 1 and SEL_CD = 1 it is the daisy-chain data input for SDO_C, and when DCEN = 0 it is connected to DGND. |
| 33 | DB0/DCIN_D | bidirectional | Data bit 0 (LSB) input/output; when DCEN = 1 and SEL_CD = 1 it is the daisy-chain data input for SDO_D, and when DCEN = 0 it is connected to DGND. |
| 34 | RANGE/XCLK | bidirectional | In hardware mode, low selects an input range of ±4 VREF and high selects ±2 VREF; in software mode it is an external or internal conversion clock pin, and it is connected to DGND if unused. |
| 35 | BUSY/INT | output | Converter busy status output that goes high at conversion start and pulses low per channel pair completion, or an interrupt output when CONFIG bit C27 = 1. |
| 36 | ASLEEP | input | Auto-sleep enable input; when high the device enters auto-sleep mode, which is recommended to save power at lower data rates. |
| 37 | CONVST_A | input | Conversion start for channel pair A; its rising edge initiates simultaneous conversion of CH_A[1:0] and resets the internal channel state machine. |
| 38 | CONVST_B | input | Conversion start for channel pair B; its rising edge initiates simultaneous conversion of CH_B[1:0]. |
| 39 | CONVST_C | input | Conversion start for channel pair C; its rising edge initiates simultaneous conversion of CH_C[1:0]. |
| 40 | CONVST_D | input | Conversion start for channel pair D; its rising edge initiates simultaneous conversion of CH_D[1:0]. |
| 41 | HW/SW | input | Mode selection input; low selects hardware mode using external pins and high selects software mode configured through the CONFIG register. |
| 42 | CH_A0 | passive | Analog input of channel A0; channel A is the master pair that is always active and must run at the highest data rate when pairs use different rates. |
| 43 | REFAP | passive | Decoupling capacitor input for the channel pair A reference, to be connected to the decoupling capacitor. |
| 44 | AGND | power_in | Analog ground; connect to the analog ground plane. |
| 45 | AVDD | power_in | Analog power supply, specified from 4.5 V to 5.5 V with 5.0 V nominal. |
| 46 | REFAN | passive | Decoupling capacitor input for the channel pair A reference, to be connected to the decoupling capacitor and AGND. |
| 47 | CH_A1 | passive | Analog input of channel A1; channel A is the master pair that is always active and must run at the highest data rate when pairs use different rates. |
| 48 | HVDD | power_in | Positive supply voltage for the analog inputs, specified from 5.0 V to 16.5 V with 15.0 V nominal. |
| 49 | CH_B0 | passive | Analog input of channel B0; input range is set by the RANGE pin or CONFIG bit C23. |
| 50 | REFBP | passive | Decoupling capacitor input for the channel pair B reference, to be connected to the decoupling capacitor. |
| 51 | AGND | power_in | Analog ground; connect to the analog ground plane. |
| 52 | AVDD | power_in | Analog power supply, specified from 4.5 V to 5.5 V with 5.0 V nominal. |
| 53 | REFBN | passive | Decoupling capacitor input for the channel pair B reference, to be connected to the decoupling capacitor and AGND. |
| 54 | CH_B1 | passive | Analog input of channel B1; input range is set by the RANGE pin or CONFIG bit C23. |
| 55 | REFN | passive | Negative reference input/output; connect to a decoupling capacitor and AGND. |
| 56 | REFIO | bidirectional | Reference voltage input/output whose value is set by the internal DAC through CONFIG bits C[9:0]; connect to a decoupling capacitor. |
| 57 | AVDD | power_in | Analog power supply, specified from 4.5 V to 5.5 V with 5.0 V nominal. |
| 58 | AGND | power_in | Analog ground; connect to the analog ground plane. |
| 59 | CH_C1 | passive | Analog input of channel C1; input range is set by the RANGE pin or CONFIG bit C21. |
| 60 | REFCN | passive | Decoupling capacitor input for the channel pair C reference, to be connected to the decoupling capacitor and AGND. |
| 61 | AVDD | power_in | Analog power supply, specified from 4.5 V to 5.5 V with 5.0 V nominal. |
| 62 | AGND | power_in | Analog ground; connect to the analog ground plane. |
| 63 | REFCP | passive | Decoupling capacitor input for the channel pair C reference, to be connected to the decoupling capacitor. |
| 64 | CH_C0 | passive | Analog input of channel C0; input range is set by the RANGE pin or CONFIG bit C21. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64-EP(9x9) |
| Category | ADC/DAC/Data Conversion |
| Pins | 65 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| HVDD to AGND supply voltage | -0.3 | 18 | V | 9 | |||
| HVSS to AGND supply voltage | -18 | 0.3 | V | 9 | |||
| AVDD to AGND supply voltage | -0.3 | 6 | V | 9 | |||
| DVDD to DGND supply voltage | -0.3 | 6 | V | 9 | |||
| Ground voltage difference AGND to DGND | -0.3 | 0.3 | V | 9 | |||
| Input current to all pins except supply | -10 | 10 | mA | 9 | |||
| Maximum virtual junction temperature | TJ | 150 | °C | 9 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 9 | ||
| Analog supply voltage | AVDD | 4.5 | 5 | 5.5 | V | 9 | |
| Buffer I/O supply voltage | DVDD | 2.7 | 3.3 | 5.5 | V | 9 | |
| Input positive supply voltage | HVDD | 5 | 15 | 16.5 | V | 9 | |
| Input negative supply voltage | HVSS | -16.5 | -15 | -5 | V | 9 | |
| Operating ambient temperature range | TA | -40 | 25 | 125 | °C | 9 | |
| Input leakage current | -1 | 1 | μA | No ongoing conversion | 10 | ||
| Reference voltage at 2.5-V operation | VREF | 2.485 | 2.5 | 2.515 | V | 2.5-V operation, REFDAC = 3FFh | 10 |
| Reference voltage at 2.5-V operation, 25°C | VREF | 2.496 | 2.5 | 2.504 | V | 2.5-V operation, REFDAC = 3FFh at 25°C | 10 |
| Reference voltage at 3.0-V operation | VREF | 2.985 | 3 | 3.015 | V | 3.0-V operation, REFDAC = 3FFh | 10 |
| Reference voltage at 3.0-V operation, 25°C | VREF | 2.995 | 3 | 3.005 | V | 3.0-V operation, REFDAC = 3FFh at 25°C | 10 |
| Reference voltage drift | dVREF/dT | -10 | 10 | ppm/°C | 10 | ||
| Reference output current | IREFOUT | -2 | 2 | mA | At dc current | 10 | |
| External load capacitance at REFIO pin | 100 | 470 | nF | At REFIO pin | 10 | ||
| External load capacitance at REF_xP, REF_xN pins | 4.7 | 10 | μF | At REF_xP, REF_xN pins | 10 | ||
| REFDAC differential nonlinearity | DNLDAC | -1 | 0.1 | 1 | LSB | 10 | |
| REFDAC integral nonlinearity | INLDAC | -2 | 0.1 | 2 | LSB | 10 | |
| REFDAC offset error | VOSDAC | -4 | 0.65 | 4 | LSB | VREF = 0.5 V (DAC = 0CDh) | 10 |
| Reference input voltage | VREFIN | 0.5 | 2.5 | 3.025 | V | 10 | |
| Digital input current | -50 | 50 | nA | VI = DVDD to DGND | 10 | ||
| High-impedance-state output current | -50 | 50 | nA | 10 | |||
| Analog supply current, ADS8568 at maximum fDATA | IAVDD | 36.6 | 48.4 | mA | ADS8568, fDATA = maximum | 11 | |
| Buffer I/O supply current at maximum fDATA | IDVDD | 0.5 | 2 | mA | fDATA = maximum | 11 | |
| Input positive supply current, ADS8568 at maximum fDATA | IHVDD | 2.3 | 3.2 | mA | ADS8568, fDATA = maximum | 11 | |
| Input negative supply current, ADS8568 at maximum fDATA | IHVSS | 2.7 | 3.6 | mA | ADS8568, fDATA = maximum | 12 | |
| Power dissipation, ADS8568 at maximum fDATA | 259.7 | 389.4 | mW | ADS8568, fDATA = maximum | 12 | ||
| Integral linearity error, VQFN, TA -40 to +85°C | INL | -3 | 1.5 | 3 | LSB | At TA = -40°C to +85°C, VQFN package (RGC) | 15 |
| Integral linearity error, VQFN, TA -40 to +125°C | INL | -4 | 1.5 | 4 | LSB | At TA = -40°C to +125°C, VQFN package (RGC) | 15 |
| Differential linearity error, TA -40 to +85°C | DNL | -1 | 0.75 | 1.75 | LSB | At TA = -40°C to +85°C | 15 |
| Differential linearity error, TA -40 to +125°C | DNL | -1 | 0.75 | 2 | LSB | At TA = -40°C to +125°C | 15 |
| Offset error | -1.5 | 0.5 | 1.5 | mV | 15 | ||
| Offset error matching | -0.65 | 0.65 | mV | 15 | |||
| Offset error drift | -3.5 | 3.5 | μV/°C | 15 | |||
| Gain error | -0.5 | 0.25 | 0.5 | % | Referenced to voltage at REFIO | 15 | |
| Gain error matching between channels of any pair | -0.2 | 0.2 | % | Between channels of any pair | 15 | ||
| Gain error matching between any two channels | -0.4 | 0.4 | % | Between any two channels | 15 | ||
| Gain error drift | -6 | 6 | ppm/°C | Referenced to voltage at REFIO | 15 | ||
| Signal-to-noise ratio, TA -40 to +85°C | SNR | 90 | 91.5 | dB | At fIN = 10 kHz, TA = -40°C to +85°C | 15 | |
| Signal-to-noise ratio, TA -40 to +125°C | SNR | 89 | 91.5 | dB | At fIN = 10 kHz, TA = -40°C to +125°C | 15 | |
| Signal-to-noise ratio and distortion, TA -40 to +85°C | SINAD | 87 | 90 | dB | At fIN = 10 kHz, TA = -40°C to +85°C | 15 | |
| Signal-to-noise ratio and distortion, TA -40 to +125°C | SINAD | 86.5 | 90 | dB | At fIN = 10 kHz, TA = -40°C to +125°C | 15 | |
| Total harmonic distortion, TA -40 to +85°C | THD | -94 | -90 | dB | At fIN = 10 kHz, TA = -40°C to +85°C | 15 | |
| Total harmonic distortion, TA -40 to +125°C | THD | -94 | -89.5 | dB | At fIN = 10 kHz, TA = -40°C to +125°C | 15 | |
| Spurious-free dynamic range, TA -40 to +85°C | SFDR | 90 | 95 | dB | At fIN = 10 kHz, TA = -40°C to +85°C | 15 | |
| Spurious-free dynamic range, TA -40 to +125°C | SFDR | 89.5 | 95 | dB | At fIN = 10 kHz, TA = -40°C to +125°C | 15 | |
| Power-supply rejection ratio, analog input | PSRR | -78 | dB | At output code FFFFh, related to HVDD and HVSS | 10 | ||
| Power-supply rejection ratio, reference | PSRR | -77 | dB | At output code FFFFh, related to AVDD | 10 | ||
| Thermal resistance, junction-to-ambient (RGC) | RθJA | 22 | °C/W | RGC (VQFN) 64 pins | 9 | ||
| Thermal resistance, junction-to-case top (RGC) | RθJC(top) | 9 | °C/W | RGC (VQFN) 64 pins | 9 | ||
| Thermal resistance, junction-to-board (RGC) | RθJB | 3.6 | °C/W | RGC (VQFN) 64 pins | 9 | ||
| Junction-to-top characterization parameter (RGC) | ψJT | 0.1 | °C/W | RGC (VQFN) 64 pins | 9 | ||
| Junction-to-board characterization parameter (RGC) | ψJB | 2.9 | °C/W | RGC (VQFN) 64 pins | 9 | ||
| Thermal resistance, junction-to-case bottom (RGC) | RθJC(bot) | 0.3 | °C/W | RGC (VQFN) 64 pins | 9 |
CAD (KiCad official)
- Symbol:
ADS8568SRGCR - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files:
ads8568srgcr-etched.step/ads8568srgcr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads8568srgcr.step/ads8568srgcr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (62 pp, sha256
79c029913ea9ce5c, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).