component
ADS8507IDW
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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"package": "SOIC-28-300mil",
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"category": "Data Acquisition",
"subcategory": "Analog To Digital Converters (ADC)",
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{
"number": "1",
"name": "R1IN",
"type": "passive",
"description": "Analog input; absolute maximum ±25 V, and its connection depends on the selected input range per Table 1 (±10 V: VIN to R1IN via 200 Ω to CAP for 0-5 V and 0-4 V ranges as listed)."
},
{
"number": "2",
"name": "AGND1",
"type": "power_in",
"description": "Analog sense ground used internally as the ground reference point, with minimal current flow through it."
},
{
"number": "3",
"name": "R2IN",
"type": "passive",
"description": "Analog input; absolute maximum ±25 V, and its connection depends on the selected input range per Table 1."
},
{
"number": "4",
"name": "CAP",
"type": "passive",
"description": "Reference buffer output that requires a 2.2-µF tantalum capacitor to ground."
},
{
"number": "5",
"name": "REF",
"type": "passive",
"description": "Reference input/output that outputs the internal 2.5-V reference or accepts an external system reference, bypassed to ground with a 2.2-µF tantalum capacitor."
},
{
"number": "6",
"name": "AGND2",
"type": "power_in",
"description": "Analog ground."
},
{
"number": "7",
"name": "SB/BTC",
"type": "input",
"description": "Selects output data format: high gives straight binary output, low gives binary 2's complement output."
},
{
"number": "8",
"name": "EXT/INT",
"type": "input",
"description": "Selects external or internal data clock: high synchronizes output data to the DATACLK input; low makes a convert command start transmission of the previous conversion's data with 16 clock pulses on DATACLK."
},
{
"number": "9",
"name": "D7",
"type": "output",
"description": "Parallel data bit 7 when BYTE is high, or bit 15 (MSB) when BYTE is low; high-impedance when CS is high and/or R/C is low, and left unconnected when using serial output."
},
{
"number": "10",
"name": "D6",
"type": "output",
"description": "Parallel data bit 6 when BYTE is high, or bit 14 when BYTE is low; high-impedance when CS is high and/or R/C is low."
},
{
"number": "11",
"name": "D5",
"type": "output",
"description": "Parallel data bit 5 when BYTE is high, or bit 13 when BYTE is low; high-impedance when CS is high and/or R/C is low."
},
{
"number": "12",
"name": "D4",
"type": "output",
"description": "Parallel data bit 4 when BYTE is high, or bit 12 when BYTE is low; high-impedance when CS is high and/or R/C is low."
},
{
"number": "13",
"name": "D3",
"type": "output",
"description": "Parallel data bit 3 when BYTE is high, or bit 11 when BYTE is low; high-impedance when CS is high and/or R/C is low."
},
{
"number": "14",
"name": "DGND",
"type": "power_in",
"description": "Digital ground."
},
{
"number": "15",
"name": "D2",
"type": "output",
"description": "Parallel data bit 2 when BYTE is high, or bit 10 when BYTE is low; high-impedance when CS is high and/or R/C is low."
},
{
"number": "16",
"name": "D1",
"type": "output",
"description": "Parallel data bit 1 when BYTE is high, or bit 9 when BYTE is low; high-impedance when CS is high and/or R/C is low."
},
{
"number": "17",
"name": "D0",
"type": "output",
"description": "Parallel data bit 0 (LSB) when BYTE is high, or bit 8 when BYTE is low; high-impedance when CS is high and/or R/C is low."
},
{
"number": "18",
"name": "DATACLK",
"type": "bidirectional",
"description": "Input or output depending on EXT/INT; output data is synchronized to it, and in internal clock mode it transmits 16 pulses after each conversion and stays low between conversions."
},
{
"number": "19",
"name": "SDATA",
"type": "output",
"description": "Serial data output synchronized to DATACLK, with format set by SB/BTC; after 16 bits in external clock mode it outputs the TAG level while CS is low and R/C is high."
},
{
"number": "20",
"name": "TAG",
"type": "input",
"description": "Tag input for external clock mode; when EXT/INT is high, its digital data is output on SDATA with a delay dependent on the external clock mode."
},
{
"number": "21",
"name": "BYTE",
"type": "input",
"description": "Selects the 8 most significant bits (low) or the 8 least significant bits (high) on the parallel output pins."
},
{
"number": "22",
"name": "R/C",
"type": "input",
"description": "Read/convert input; with CS low, a falling edge puts the sample-and-hold into hold and starts a conversion, and in internal clock mode it also initiates transmission of the previous result."
},
{
"number": "23",
"name": "CS",
"type": "input",
"description": "Chip select, internally ORed with R/C; with R/C low, a falling edge starts a new conversion, and in internal clock mode it starts serial transmission of the previous result."
},
{
"number": "24",
"name": "BUSY",
"type": "output",
"description": "Goes low at the start of a conversion and stays low until the conversion is complete and the digital outputs are updated."
},
{
"number": "25",
"name": "PWRD",
"type": "input",
"description": "Power-down input; when high, conversions are inhibited and power consumption is significantly reduced while the previous result is held in the output shift register (power-down mode is 50 µW max per the specification)."
},
{
"number": "26",
"name": "REFD",
"type": "input",
"description": "Reference disable input; when high it shuts down the internal reference, so an external reference is required for conversions (REFD high power is 20 mW per the specification)."
},
{
"number": "27",
"name": "VANA",
"type": "power_in",
"description": "Analog supply, nominally +5 V (4.75 V to 5.25 V per the specification), to be decoupled with 0.1-µF ceramic and 10-µF tantalum capacitors; absolute maximum 6 V."
},
{
"number": "28",
"name": "VDIG",
"type": "power_in",
"description": "Digital supply, nominally +5 V; connect directly to pin 27 and it must be less than or equal to VANA."
}
],
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"guards": "pin_guards 0.1: passed",
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