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ADS8507IDW

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Texas Instruments Analog To Digital Converters (ADC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS8507IDW

Texas Instruments · Analog To Digital Converters (ADC) · SOIC-28-300mil

ADS8507IDW from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 R1IN passive Analog input; absolute maximum ±25 V, and its connection depends on the selected input range per Table 1 (±10 V: VIN to R1IN via 200 Ω to CAP for 0-5 V and 0-4 V ranges as listed).
2 AGND1 power_in Analog sense ground used internally as the ground reference point, with minimal current flow through it.
3 R2IN passive Analog input; absolute maximum ±25 V, and its connection depends on the selected input range per Table 1.
4 CAP passive Reference buffer output that requires a 2.2-µF tantalum capacitor to ground.
5 REF passive Reference input/output that outputs the internal 2.5-V reference or accepts an external system reference, bypassed to ground with a 2.2-µF tantalum capacitor.
6 AGND2 power_in Analog ground.
7 SB/BTC input Selects output data format: high gives straight binary output, low gives binary 2's complement output.
8 EXT/INT input Selects external or internal data clock: high synchronizes output data to the DATACLK input; low makes a convert command start transmission of the previous conversion's data with 16 clock pulses on DATACLK.
9 D7 output Parallel data bit 7 when BYTE is high, or bit 15 (MSB) when BYTE is low; high-impedance when CS is high and/or R/C is low, and left unconnected when using serial output.
10 D6 output Parallel data bit 6 when BYTE is high, or bit 14 when BYTE is low; high-impedance when CS is high and/or R/C is low.
11 D5 output Parallel data bit 5 when BYTE is high, or bit 13 when BYTE is low; high-impedance when CS is high and/or R/C is low.
12 D4 output Parallel data bit 4 when BYTE is high, or bit 12 when BYTE is low; high-impedance when CS is high and/or R/C is low.
13 D3 output Parallel data bit 3 when BYTE is high, or bit 11 when BYTE is low; high-impedance when CS is high and/or R/C is low.
14 DGND power_in Digital ground.
15 D2 output Parallel data bit 2 when BYTE is high, or bit 10 when BYTE is low; high-impedance when CS is high and/or R/C is low.
16 D1 output Parallel data bit 1 when BYTE is high, or bit 9 when BYTE is low; high-impedance when CS is high and/or R/C is low.
17 D0 output Parallel data bit 0 (LSB) when BYTE is high, or bit 8 when BYTE is low; high-impedance when CS is high and/or R/C is low.
18 DATACLK bidirectional Input or output depending on EXT/INT; output data is synchronized to it, and in internal clock mode it transmits 16 pulses after each conversion and stays low between conversions.
19 SDATA output Serial data output synchronized to DATACLK, with format set by SB/BTC; after 16 bits in external clock mode it outputs the TAG level while CS is low and R/C is high.
20 TAG input Tag input for external clock mode; when EXT/INT is high, its digital data is output on SDATA with a delay dependent on the external clock mode.
21 BYTE input Selects the 8 most significant bits (low) or the 8 least significant bits (high) on the parallel output pins.
22 R/C input Read/convert input; with CS low, a falling edge puts the sample-and-hold into hold and starts a conversion, and in internal clock mode it also initiates transmission of the previous result.
23 CS input Chip select, internally ORed with R/C; with R/C low, a falling edge starts a new conversion, and in internal clock mode it starts serial transmission of the previous result.
24 BUSY output Goes low at the start of a conversion and stays low until the conversion is complete and the digital outputs are updated.
25 PWRD input Power-down input; when high, conversions are inhibited and power consumption is significantly reduced while the previous result is held in the output shift register (power-down mode is 50 µW max per the specification).
26 REFD input Reference disable input; when high it shuts down the internal reference, so an external reference is required for conversions (REFD high power is 20 mW per the specification).
27 VANA power_in Analog supply, nominally +5 V (4.75 V to 5.25 V per the specification), to be decoupled with 0.1-µF ceramic and 10-µF tantalum capacitors; absolute maximum 6 V.
28 VDIG power_in Digital supply, nominally +5 V; connect directly to pin 27 and it must be less than or equal to VANA.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-28-300mil
Category Data Acquisition
Pins 28

CAD (KiCad official)

  • Symbol: ADS8507IDW
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: ads8507idw-etched.step / ads8507idw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8507idw.step / ads8507idw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 b4887a0099e083eb, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF