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ADS8507IBDWR
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADCs), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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ADS8507IBDWR
Texas Instruments · Analog To Digital Converters (ADCs) · SOIC-28-300mil
ADS8507IBDWR from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | R1IN | input | Analog input; the input range is set by how R1IN is connected per Table 1 (for ±10 V it connects to VIN via 200 Ω, for 0 to 5 V it connects to AGND, and for 0 to 4 V it connects to VIN via 200 Ω... see note). |
| 2 | AGND1 | power_in | Analog sense ground used internally as the ground reference point, with minimal current flow. |
| 3 | R2IN | input | Analog input; the input range is set by how R2IN is connected per Table 1. |
| 4 | CAP | passive | Reference buffer output that requires a 2.2-µF tantalum capacitor to ground. |
| 5 | REF | bidirectional | Reference input/output that outputs the internal 2.5-V reference or can be driven by an external reference, and must be bypassed to ground with a 2.2-µF tantalum capacitor in both cases. |
| 6 | AGND2 | power_in | Analog ground. |
| 7 | SB/BTC | input | Selects the output data format: high gives straight binary output and low gives binary 2's complement output. |
| 8 | EXT/INT | input | Selects the external or internal data clock: high synchronizes output data to the DATACLK input, and low makes a convert command start transmission of the previous conversion's data with 16 clock pulses on DATACLK. |
| 9 | D7 | tri_state | Parallel data bit 7 when BYTE is high or bit 15 (MSB) when BYTE is low; high impedance when CS is high and/or R/C is low, and leave unconnected when using serial output. |
| 10 | D6 | tri_state | Parallel data bit 6 when BYTE is high or bit 14 when BYTE is low; high impedance when CS is high and/or R/C is low. |
| 11 | D5 | tri_state | Parallel data bit 5 when BYTE is high or bit 13 when BYTE is low; high impedance when CS is high and/or R/C is low. |
| 12 | D4 | tri_state | Parallel data bit 4 when BYTE is high or bit 12 when BYTE is low; high impedance when CS is high and/or R/C is low. |
| 13 | D3 | tri_state | Parallel data bit 3 when BYTE is high or bit 11 when BYTE is low; high impedance when CS is high and/or R/C is low. |
| 14 | DGND | power_in | Digital ground. |
| 15 | D2 | tri_state | Parallel data bit 2 when BYTE is high or bit 10 when BYTE is low; high impedance when CS is high and/or R/C is low. |
| 16 | D1 | tri_state | Parallel data bit 1 when BYTE is high or bit 9 when BYTE is low; high impedance when CS is high and/or R/C is low. |
| 17 | D0 | tri_state | Parallel data bit 0 (LSB) when BYTE is high or bit 8 when BYTE is low; high impedance when CS is high and/or R/C is low. |
| 18 | DATACLK | bidirectional | Input or output depending on the EXT/INT level; output data is synchronized to it, and in external-clock-off mode (EXT/INT low) it transmits 16 pulses after each conversion and stays low between conversions. |
| 19 | SDATA | output | Serial data output synchronized to DATACLK with format set by SB/BTC; after 16 bits in external clock mode it outputs the TAG input level while CS is low and R/C is high. |
| 20 | TAG | input | Tag input for the external clock mode whose digital level is output on SDATA after the 16 data bits, with a delay that depends on the external clock mode. |
| 21 | BYTE | input | Selects the 8 most significant bits (low) or the 8 least significant bits (high) on the parallel output pins. |
| 22 | R/C | input | Read/convert input: with CS low, a falling edge puts the sample-and-hold into hold and starts a conversion, and when EXT/INT is low it also initiates transmission of the previous conversion's data. |
| 23 | CS | input | Chip select internally ORed with R/C; when R/C is low, a falling edge starts a new conversion, and if EXT/INT is low the same edge starts serial transmission of the previous result. |
| 24 | BUSY | output | Goes low at the start of a conversion and stays low until the conversion is complete and the digital outputs have been updated. |
| 25 | PWRD | input | Power-down input: when high, conversions are inhibited and power consumption is significantly reduced while previous results are held in the output shift register. |
| 26 | REFD | input | When high, shuts down the internal reference, so an external reference is required for conversions. |
| 27 | VANA | power_in | Analog supply, nominally +5 V; decouple with 0.1-µF ceramic and 10-µF tantalum capacitors. |
| 28 | VDIG | power_in | Digital supply, nominally +5 V, connected directly to pin 27; must be less than or equal to VANA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-28-300mil |
| Category | ADC/DAC/Data Conversion |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog input R1IN, absolute voltage | -25 | 25 | V | 2 | |||
| Analog input R2IN, absolute voltage | -25 | 25 | V | 2 | |||
| Ground voltage differences (DGND, AGND2) | -0.3 | 0.3 | V | 2 | |||
| Analog supply VANA, absolute maximum | VANA | 6 | V | 2 | |||
| Digital supply VDIG, absolute maximum | VDIG | 6 | V | 2 | |||
| Maximum junction temperature | 165 | °C | 2 | ||||
| Storage temperature range | -65 | 150 | °C | 2 | |||
| Internal power dissipation | 700 | mW | 2 | ||||
| Lead temperature (soldering) | 260 | °C | Soldering, 1.6 mm from case, 10 seconds | 2 | |||
| Voltage range, ±10 V input range | -10 | 10 | V | See Table 1 | 2 | ||
| Voltage range, 0 V to 5 V input range | 0 | 5 | V | See Table 1 | 2 | ||
| Voltage range, 0 V to 4 V input range | 0 | 4 | V | See Table 1 | 2 | ||
| Integral linearity error (INL) | INL | -1.5 | 1.5 | LSB | 2 | ||
| Differential linearity error (DNL) | DNL | -1 | 1.5 | LSB | 3 | ||
| Gain error | -0.1 | 0.1 | % | 3 | |||
| Full scale error | -0.25 | 0.25 | % | 3 | |||
| Full scale error drift | -5 | 5 | ppm/°C | 3 | |||
| Full scale error, external 2.5-V reference | -0.25 | 0.25 | % | Ext. 2.5-V Ref | 3 | ||
| Full scale error drift, external 2.5-V reference | -0.5 | 0.5 | ppm/°C | Ext. 2.5-V Ref | 3 | ||
| Bipolar zero error | -5 | 5 | mV | ±10 V Range | 3 | ||
| Bipolar zero error drift | -0.5 | 0.5 | ppm/°C | ±10 V Range | 3 | ||
| Unipolar zero error | -3 | 3 | mV | 0 V to 5 V, 0 V to 4 V Ranges | 3 | ||
| Unipolar zero error drift | -0.5 | 0.5 | ppm/°C | 0 V to 5 V, 0 V to 4 V Ranges | 3 | ||
| Power supply sensitivity | -8 | 8 | LSB | +4.75 V < VS < +5.25 V (VDIG = VANA = VS) | 3 | ||
| Spurious-free dynamic range (SFDR) | 96 | 102 | dB | fIN = 1 kHz, ±10 V | 3 | ||
| Signal-to-(noise+distortion) (SINAD) | SINAD | 87 | 89.9 | dB | fIN = 1 kHz, ±10 V | 3 | |
| Signal-to-noise (SNR) | SNR | 87 | 89.9 | dB | 3 | ||
| Internal reference voltage | 2.48 | 2.5 | 2.52 | V | No load | 3 | |
| External reference voltage range for specified linearity | 2.3 | 2.5 | 2.7 | V | 3 | ||
| Low-level input voltage | VIL | -0.3 | 0.8 | V | 3 | ||
| High-level input voltage | VIH | 2 | V | 3 | |||
| Low-level input current | IIL | -10 | 10 | µA | VIL = 0 V | 4 | |
| High-level input current | IIH | -10 | 10 | µA | VIH = 5 V | 4 | |
| High-Z state leakage current | -5 | 5 | µA | High-Z state, VOUT = 0 V to VDIG | 4 | ||
| Digital voltage | VDIG | 4.75 | 5 | 5.25 | V | Must be ≤ VANA | 4 |
| Analog voltage | VANA | 4.75 | 5 | 5.25 | V | 4 | |
| Power dissipation | 24 | 30 | mW | VANA = VDIG = 5 V, fS = 40 kHz | 4 | ||
| Power dissipation in power-down mode | 50 | µW | PWRD and REFD High | 4 | |||
| Specified performance temperature range | -40 | 85 | °C | 4 | |||
| Derated performance temperature range | -55 | 125 | °C | 4 | |||
| SO package thermal resistance (ΘJA) | ΘJA | 46 | °C/W | SO package | 4 |
CAD (KiCad official)
- Symbol:
ADS8507IBDWR - Footprint:
Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm - 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
- 3D model files:
ads8507ibdwr-etched.step/ads8507ibdwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads8507ibdwr.step/ads8507ibdwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (37 pp, sha256
b186789b078b48ab, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).