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ADS4229IRGCT

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Texas Instruments Analog To Digital Converters (ADC), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADS4229IRGCT

Texas Instruments · Analog To Digital Converters (ADC) · VQFN-64-EP(9x9)

ADS4229IRGCT from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRVDD power_in Output buffer supply, 1.7 V to 1.9 V (1.8 V nominal).
2 DB2M output Channel B LVDS differential output data D2/D3 multiplexed, complement; in CMOS mode this pin is DB2 (CMOS data bit D2), CMOS levels from DRVDD.
3 DB2P output Channel B LVDS differential output data D2/D3 multiplexed, true; in CMOS mode this pin is DB3 (CMOS data bit D3).
4 DB4M output Channel B LVDS differential output data D4/D5 multiplexed, complement; in CMOS mode this pin is DB4 (CMOS data bit D4).
5 DB4P output Channel B LVDS differential output data D4/D5 multiplexed, true; in CMOS mode this pin is DB5 (CMOS data bit D5).
6 DB6M output Channel B LVDS differential output data D6/D7 multiplexed, complement; in CMOS mode this pin is DB6 (CMOS data bit D6).
7 DB6P output Channel B LVDS differential output data D6/D7 multiplexed, true; in CMOS mode this pin is DB7 (CMOS data bit D7).
8 DB8M output Channel B LVDS differential output data D8/D9 multiplexed, complement; in CMOS mode this pin is DB8 (CMOS data bit D8).
9 DB8P output Channel B LVDS differential output data D8/D9 multiplexed, true; in CMOS mode this pin is DB9 (CMOS data bit D9).
10 DB10M output Channel B LVDS differential output data D10/D11 multiplexed, complement; in CMOS mode this pin is DB10 (CMOS data bit D10).
11 DB10P output Channel B LVDS differential output data D10/D11 multiplexed, true; in CMOS mode this pin is DB11 (CMOS data bit D11).
12 RESET input Serial interface reset input; apply a high pulse wider than 10 ns for hardware reset, must be tied high in parallel mode, and has an internal 150-kΩ pull-down.
13 SCLK input Serial interface clock when RESET is low, or low-speed mode select when RESET is tied high; has an internal 150-kΩ pull-down.
14 SDATA input Serial interface data input with an internal 150-kΩ pull-down.
15 SEN input Serial interface enable when RESET is low, or output data format and interface select when RESET is tied high; has an internal 150-kΩ pull-up to AVDD.
16 AVDD power_in Analog supply, 1.7 V to 1.9 V (1.8 V nominal).
17 AGND power_in Analog ground.
18 AGND power_in Analog ground.
19 INP_B input Channel B differential analog positive input; differential input range 2 VPP with input common mode VCM ±0.05 V.
20 INM_B input Channel B differential analog negative input; differential input range 2 VPP with input common mode VCM ±0.05 V.
21 AGND power_in Analog ground.
22 AVDD power_in Analog supply, 1.7 V to 1.9 V (1.8 V nominal).
23 VCM output Common-mode voltage output (0.95 V nominal, 0.87 V in high-speed mode) for external biasing of the analog inputs.
24 AGND power_in Analog ground.
25 CLKP input Differential clock positive input; sine wave 0.2 to 1.5 VPP AC-coupled, or LVPECL, LVDS or LVCMOS levels, sample rate 80 to 250 MSPS (low-speed mode 1 to 80 MSPS).
26 CLKM input Differential clock negative input; use with CLKP as the differential sampling clock pair (clock duty cycle 35% to 65%).
27 AGND power_in Analog ground.
28 AGND power_in Analog ground.
29 INP_A input Channel A differential analog positive input; differential input range 2 VPP with input common mode VCM ±0.05 V.
30 INM_A input Channel A differential analog negative input; differential input range 2 VPP with input common mode VCM ±0.05 V.
31 AGND power_in Analog ground.
32 AGND power_in Analog ground.
33 AVDD power_in Analog supply, 1.7 V to 1.9 V (1.8 V nominal).
34 AVDD power_in Analog supply, 1.7 V to 1.9 V (1.8 V nominal).
35 CTRL1 input Digital control input which, together with CTRL2 and CTRL3, selects power-down modes (for example, CTRL1 high with CTRL2 and CTRL3 low gives global power-down).
36 CTRL2 input Digital control input which, together with CTRL1 and CTRL3, selects power-down modes.
37 CTRL3 input Digital control input which, together with CTRL1 and CTRL2, selects power-down and multiplexed-mode operation.
38 NC unconnected Do not connect; must be floated.
39 NC unconnected Do not connect; must be floated.
40 NC unconnected Do not connect; must be floated.
41 NC unconnected Do not connect; must be floated.
42 DA0M output Channel A LVDS differential output data D0/D1 multiplexed, complement; in CMOS mode this pin is DA0 (CMOS data bit D0).
43 DA0P output Channel A LVDS differential output data D0/D1 multiplexed, true; in CMOS mode this pin is DA1 (CMOS data bit D1).
44 DA2M output Channel A LVDS differential output data D2/D3 multiplexed, complement; in CMOS mode this pin is DA2 (CMOS data bit D2).
45 DA2P output Channel A LVDS differential output data D2/D3 multiplexed, true; in CMOS mode this pin is DA3 (CMOS data bit D3).
46 DA4M output Channel A LVDS differential output data D4/D5 multiplexed, complement; in CMOS mode this pin is DA4 (CMOS data bit D4).
47 DA4P output Channel A LVDS differential output data D4/D5 multiplexed, true; in CMOS mode this pin is DA5 (CMOS data bit D5).
48 DRVDD power_in Output buffer supply, 1.7 V to 1.9 V (1.8 V nominal).
49 DRGND power_in Output buffer ground; the PowerPAD is connected to DRGND.
50 DA6M output Channel A LVDS differential output data D6/D7 multiplexed, complement; in CMOS mode this pin is DA6 (CMOS data bit D6).
51 DA6P output Channel A LVDS differential output data D6/D7 multiplexed, true; in CMOS mode this pin is DA7 (CMOS data bit D7).
52 DA8M output Channel A LVDS differential output data D8/D9 multiplexed, complement; in CMOS mode this pin is DA8 (CMOS data bit D8).
53 DA8P output Channel A LVDS differential output data D8/D9 multiplexed, true; in CMOS mode this pin is DA9 (CMOS data bit D9).
54 DA10M output Channel A LVDS differential output data D10/D11 multiplexed, complement; in CMOS mode this pin is DA10 (CMOS data bit D10).
55 DA10P output Channel A LVDS differential output data D10/D11 multiplexed, true; in CMOS mode this pin is DA11 (CMOS data bit D11).
56 CLKOUTM output Differential LVDS output clock, complement; in CMOS mode this pin is UNUSED.
57 CLKOUTP output Differential LVDS output clock, true; in CMOS mode this pin is CLKOUT, the CMOS output clock.
58 NC unconnected Do not connect; must be floated.
59 NC unconnected Do not connect; must be floated.
60 NC unconnected Do not connect; must be floated.
61 NC unconnected Do not connect; must be floated.
62 DB0M output Channel B LVDS differential output data D0/D1 multiplexed, complement; in CMOS mode this pin is DB0 (CMOS data bit D0).
63 DB0P output Channel B LVDS differential output data D0/D1 multiplexed, true; in CMOS mode this pin is DB1 (CMOS data bit D1).
64 SDOUT output Serial register readout output when READOUT is enabled, CMOS levels from DRVDD; high-impedance when READOUT = 0.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category Data Acquisition
Pins 65

CAD (KiCad official)

  • Symbol: ADS4229IRGCT
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ads4229irgct-etched.step / ads4229irgct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads4229irgct.step / ads4229irgct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (68 pp, sha256 47833104b1baa2ae, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF