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ADS4229IRGCT
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Texas Instruments Analog To Digital Converters (ADC), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+102@@ -0,0 +1,102 @@+# ADS4229IRGCT++**Texas Instruments** · Analog To Digital Converters (ADC) · VQFN-64-EP(9x9)++ADS4229IRGCT from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DRVDD | power_in | Output buffer supply, 1.7 V to 1.9 V (1.8 V nominal). |+| 2 | DB2M | output | Channel B LVDS differential output data D2/D3 multiplexed, complement; in CMOS mode this pin is DB2 (CMOS data bit D2), CMOS levels from DRVDD. |+| 3 | DB2P | output | Channel B LVDS differential output data D2/D3 multiplexed, true; in CMOS mode this pin is DB3 (CMOS data bit D3). |+| 4 | DB4M | output | Channel B LVDS differential output data D4/D5 multiplexed, complement; in CMOS mode this pin is DB4 (CMOS data bit D4). |+| 5 | DB4P | output | Channel B LVDS differential output data D4/D5 multiplexed, true; in CMOS mode this pin is DB5 (CMOS data bit D5). |+| 6 | DB6M | output | Channel B LVDS differential output data D6/D7 multiplexed, complement; in CMOS mode this pin is DB6 (CMOS data bit D6). |+| 7 | DB6P | output | Channel B LVDS differential output data D6/D7 multiplexed, true; in CMOS mode this pin is DB7 (CMOS data bit D7). |+| 8 | DB8M | output | Channel B LVDS differential output data D8/D9 multiplexed, complement; in CMOS mode this pin is DB8 (CMOS data bit D8). |+| 9 | DB8P | output | Channel B LVDS differential output data D8/D9 multiplexed, true; in CMOS mode this pin is DB9 (CMOS data bit D9). |+| 10 | DB10M | output | Channel B LVDS differential output data D10/D11 multiplexed, complement; in CMOS mode this pin is DB10 (CMOS data bit D10). |+| 11 | DB10P | output | Channel B LVDS differential output data D10/D11 multiplexed, true; in CMOS mode this pin is DB11 (CMOS data bit D11). |+| 12 | RESET | input | Serial interface reset input; apply a high pulse wider than 10 ns for hardware reset, must be tied high in parallel mode, and has an internal 150-kΩ pull-down. |+| 13 | SCLK | input | Serial interface clock when RESET is low, or low-speed mode select when RESET is tied high; has an internal 150-kΩ pull-down. |+| 14 | SDATA | input | Serial interface data input with an internal 150-kΩ pull-down. |+| 15 | SEN | input | Serial interface enable when RESET is low, or output data format and interface select when RESET is tied high; has an internal 150-kΩ pull-up to AVDD. |+| 16 | AVDD | power_in | Analog supply, 1.7 V to 1.9 V (1.8 V nominal). |+| 17 | AGND | power_in | Analog ground. |+| 18 | AGND | power_in | Analog ground. |+| 19 | INP_B | input | Channel B differential analog positive input; differential input range 2 VPP with input common mode VCM ±0.05 V. |+| 20 | INM_B | input | Channel B differential analog negative input; differential input range 2 VPP with input common mode VCM ±0.05 V. |+| 21 | AGND | power_in | Analog ground. |+| 22 | AVDD | power_in | Analog supply, 1.7 V to 1.9 V (1.8 V nominal). |+| 23 | VCM | output | Common-mode voltage output (0.95 V nominal, 0.87 V in high-speed mode) for external biasing of the analog inputs. |+| 24 | AGND | power_in | Analog ground. |+| 25 | CLKP | input | Differential clock positive input; sine wave 0.2 to 1.5 VPP AC-coupled, or LVPECL, LVDS or LVCMOS levels, sample rate 80 to 250 MSPS (low-speed mode 1 to 80 MSPS). |+| 26 | CLKM | input | Differential clock negative input; use with CLKP as the differential sampling clock pair (clock duty cycle 35% to 65%). |+| 27 | AGND | power_in | Analog ground. |+| 28 | AGND | power_in | Analog ground. |+| 29 | INP_A | input | Channel A differential analog positive input; differential input range 2 VPP with input common mode VCM ±0.05 V. |+| 30 | INM_A | input | Channel A differential analog negative input; differential input range 2 VPP with input common mode VCM ±0.05 V. |+| 31 | AGND | power_in | Analog ground. |+| 32 | AGND | power_in | Analog ground. |+| 33 | AVDD | power_in | Analog supply, 1.7 V to 1.9 V (1.8 V nominal). |+| 34 | AVDD | power_in | Analog supply, 1.7 V to 1.9 V (1.8 V nominal). |+| 35 | CTRL1 | input | Digital control input which, together with CTRL2 and CTRL3, selects power-down modes (for example, CTRL1 high with CTRL2 and CTRL3 low gives global power-down). |+| 36 | CTRL2 | input | Digital control input which, together with CTRL1 and CTRL3, selects power-down modes. |+| 37 | CTRL3 | input | Digital control input which, together with CTRL1 and CTRL2, selects power-down and multiplexed-mode operation. |+| 38 | NC | unconnected | Do not connect; must be floated. |+| 39 | NC | unconnected | Do not connect; must be floated. |+| 40 | NC | unconnected | Do not connect; must be floated. |+| 41 | NC | unconnected | Do not connect; must be floated. |+| 42 | DA0M | output | Channel A LVDS differential output data D0/D1 multiplexed, complement; in CMOS mode this pin is DA0 (CMOS data bit D0). |+| 43 | DA0P | output | Channel A LVDS differential output data D0/D1 multiplexed, true; in CMOS mode this pin is DA1 (CMOS data bit D1). |+| 44 | DA2M | output | Channel A LVDS differential output data D2/D3 multiplexed, complement; in CMOS mode this pin is DA2 (CMOS data bit D2). |+| 45 | DA2P | output | Channel A LVDS differential output data D2/D3 multiplexed, true; in CMOS mode this pin is DA3 (CMOS data bit D3). |+| 46 | DA4M | output | Channel A LVDS differential output data D4/D5 multiplexed, complement; in CMOS mode this pin is DA4 (CMOS data bit D4). |+| 47 | DA4P | output | Channel A LVDS differential output data D4/D5 multiplexed, true; in CMOS mode this pin is DA5 (CMOS data bit D5). |+| 48 | DRVDD | power_in | Output buffer supply, 1.7 V to 1.9 V (1.8 V nominal). |+| 49 | DRGND | power_in | Output buffer ground; the PowerPAD is connected to DRGND. |+| 50 | DA6M | output | Channel A LVDS differential output data D6/D7 multiplexed, complement; in CMOS mode this pin is DA6 (CMOS data bit D6). |+| 51 | DA6P | output | Channel A LVDS differential output data D6/D7 multiplexed, true; in CMOS mode this pin is DA7 (CMOS data bit D7). |+| 52 | DA8M | output | Channel A LVDS differential output data D8/D9 multiplexed, complement; in CMOS mode this pin is DA8 (CMOS data bit D8). |+| 53 | DA8P | output | Channel A LVDS differential output data D8/D9 multiplexed, true; in CMOS mode this pin is DA9 (CMOS data bit D9). |+| 54 | DA10M | output | Channel A LVDS differential output data D10/D11 multiplexed, complement; in CMOS mode this pin is DA10 (CMOS data bit D10). |+| 55 | DA10P | output | Channel A LVDS differential output data D10/D11 multiplexed, true; in CMOS mode this pin is DA11 (CMOS data bit D11). |+| 56 | CLKOUTM | output | Differential LVDS output clock, complement; in CMOS mode this pin is UNUSED. |+| 57 | CLKOUTP | output | Differential LVDS output clock, true; in CMOS mode this pin is CLKOUT, the CMOS output clock. |+| 58 | NC | unconnected | Do not connect; must be floated. |+| 59 | NC | unconnected | Do not connect; must be floated. |+| 60 | NC | unconnected | Do not connect; must be floated. |+| 61 | NC | unconnected | Do not connect; must be floated. |+| 62 | DB0M | output | Channel B LVDS differential output data D0/D1 multiplexed, complement; in CMOS mode this pin is DB0 (CMOS data bit D0). |+| 63 | DB0P | output | Channel B LVDS differential output data D0/D1 multiplexed, true; in CMOS mode this pin is DB1 (CMOS data bit D1). |+| 64 | SDOUT | output | Serial register readout output when READOUT is enabled, CMOS levels from DRVDD; high-impedance when READOUT = 0. |+| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-64-EP(9x9) |+| Category | Data Acquisition |+| Pins | 65 |++## CAD (KiCad official)++- Symbol: `ADS4229IRGCT`+- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`+- 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)+- 3D model files: `ads4229irgct-etched.step` / `ads4229irgct-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads4229irgct.step` / `ads4229irgct.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads4229) (68 pp, sha256 `47833104b1baa2ae`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ads4229irgct-datasheet.pdf)
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in CMOS mode this pin is DB2 (CMOS data bit D2), CMOS levels from DRVDD."+ },+ {+ "number": "3",+ "name": "DB2P",+ "type": "output",+ "description": "Channel B LVDS differential output data D2/D3 multiplexed, true; in CMOS mode this pin is DB3 (CMOS data bit D3)."+ },+ {+ "number": "4",+ "name": "DB4M",+ "type": "output",+ "description": "Channel B LVDS differential output data D4/D5 multiplexed, complement; in CMOS mode this pin is DB4 (CMOS data bit D4)."+ },+ {+ "number": "5",+ "name": "DB4P",+ "type": "output",+ "description": "Channel B LVDS differential output data D4/D5 multiplexed, true; in CMOS mode this pin is DB5 (CMOS data bit D5)."+ },+ {+ "number": "6",+ "name": "DB6M",+ "type": "output",+ "description": "Channel B LVDS differential output data D6/D7 multiplexed, complement; in CMOS mode this pin is DB6 (CMOS data bit D6)."+ },+ {+ "number": "7",+ "name": "DB6P",+ "type": "output",+ "description": "Channel B LVDS differential output data D6/D7 multiplexed, true; in CMOS mode this pin is DB7 (CMOS data bit D7)."+ },+ {+ "number": "8",+ "name": "DB8M",+ "type": "output",+ "description": "Channel B LVDS differential output data D8/D9 multiplexed, complement; in CMOS mode this pin is DB8 (CMOS data bit D8)."+ },+ {+ "number": "9",+ "name": "DB8P",+ "type": "output",+ "description": "Channel B LVDS differential output data D8/D9 multiplexed, true; in CMOS mode this pin is DB9 (CMOS data bit D9)."+ },+ {+ "number": "10",+ "name": "DB10M",+ "type": "output",+ "description": "Channel B LVDS differential output data D10/D11 multiplexed, complement; in CMOS mode this pin is DB10 (CMOS data bit D10)."+ },+ {+ "number": "11",+ "name": "DB10P",+ "type": "output",+ "description": "Channel B LVDS differential output data D10/D11 multiplexed, true; in CMOS mode this pin is DB11 (CMOS data bit D11)."+ },+ {+ "number": "12",+ "name": "RESET",+ "type": "input",+ "description": "Serial interface reset input; apply a high pulse wider than 10 ns for hardware reset, must be tied high in parallel mode, and has an internal 150-kΩ pull-down."+ },+ {+ "number": "13",+ "name": "SCLK",+ "type": "input",+ "description": "Serial interface clock when RESET is low, or low-speed mode select when RESET is tied high; has an internal 150-kΩ pull-down."+ },+ {+ "number": "14",+ "name": "SDATA",+ "type": "input",+ "description": "Serial interface data input with an internal 150-kΩ pull-down."+ },+ {+ "number": "15",+ "name": "SEN",+ "type": "input",+ "description": "Serial interface enable when RESET is low, or output data format and interface select when RESET is tied high; has an internal 150-kΩ pull-up to AVDD."+ },+ {+ "number": "16",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply, 1.7 V to 1.9 V (1.8 V nominal)."+ },+ {+ "number": "17",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "18",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "19",+ "name": "INP_B",+ "type": "input",+ "description": "Channel B differential analog positive input; differential input range 2 VPP with input common mode VCM ±0.05 V."+ },+ {+ "number": "20",+ "name": "INM_B",+ "type": "input",+ "description": "Channel B differential analog negative input; differential input range 2 VPP with input common mode VCM ±0.05 V."+ },+ {+ "number": "21",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "22",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply, 1.7 V to 1.9 V (1.8 V nominal)."+ },+ {+ "number": "23",+ "name": "VCM",+ "type": "output",+ "description": "Common-mode voltage output (0.95 V nominal, 0.87 V in high-speed mode) for external biasing of the analog inputs."+ },+ {+ "number": "24",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "25",+ "name": "CLKP",+ "type": "input",+ "description": "Differential clock positive input; sine wave 0.2 to 1.5 VPP AC-coupled, or LVPECL, LVDS or LVCMOS levels, sample rate 80 to 250 MSPS (low-speed mode 1 to 80 MSPS)."+ },+ {+ "number": "26",+ "name": "CLKM",+ "type": "input",+ "description": "Differential clock negative input; use with CLKP as the differential sampling clock pair (clock duty cycle 35% to 65%)."+ },+ {+ "number": "27",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "28",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "29",+ "name": "INP_A",+ "type": "input",+ "description": "Channel A differential analog positive input; differential input range 2 VPP with input common mode VCM ±0.05 V."+ },+ {+ "number": "30",+ "name": "INM_A",+ "type": "input",+ "description": "Channel A differential analog negative input; differential input range 2 VPP with input common mode VCM ±0.05 V."+ },+ {+ "number": "31",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "32",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "33",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply, 1.7 V to 1.9 V (1.8 V nominal)."+ },+ {+ "number": "34",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply, 1.7 V to 1.9 V (1.8 V nominal)."+ },+ {+ "number": "35",+ "name": "CTRL1",+ "type": "input",+ "description": "Digital control input which, together with CTRL2 and CTRL3, selects power-down modes (for example, CTRL1 high with CTRL2 and CTRL3 low gives global power-down)."+ },+ {+ "number": "36",+ "name": "CTRL2",+ "type": "input",+ "description": "Digital control input which, together with CTRL1 and CTRL3, selects power-down modes."+ },+ {+ "number": "37",+ "name": "CTRL3",+ "type": "input",+ "description": "Digital control input which, together with CTRL1 and CTRL2, selects power-down and multiplexed-mode operation."+ },+ {+ "number": "38",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect; must be floated."+ },+ {+ "number": "39",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect; must be floated."+ },+ {+ "number": "40",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect; must be floated."+ },+ {+ "number": "41",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect; must be floated."+ },+ {+ "number": "42",+ "name": "DA0M",+ "type": "output",+ "description": "Channel A LVDS differential output data D0/D1 multiplexed, complement; in CMOS mode this pin is DA0 (CMOS data bit D0)."+ },+ {+ "number": "43",+ "name": "DA0P",+ "type": "output",+ "description": "Channel A LVDS differential output data D0/D1 multiplexed, true; in CMOS mode this pin is DA1 (CMOS data bit D1)."+ },+ {+ "number": "44",+ "name": "DA2M",+ "type": "output",+ "description": "Channel A LVDS differential output data D2/D3 multiplexed, complement; in CMOS mode this pin is DA2 (CMOS data bit D2)."+ },+ {+ "number": "45",+ "name": "DA2P",+ "type": "output",+ "description": "Channel A LVDS differential output data D2/D3 multiplexed, true; in CMOS mode this pin is DA3 (CMOS data bit D3)."+ },+ {+ "number": "46",+ "name": "DA4M",+ "type": "output",+ "description": "Channel A LVDS differential output data D4/D5 multiplexed, complement; in CMOS mode this pin is DA4 (CMOS data bit D4)."+ },+ {+ "number": "47",+ "name": "DA4P",+ "type": "output",+ "description": "Channel A LVDS differential output data D4/D5 multiplexed, true; in CMOS mode this pin is DA5 (CMOS data bit D5)."+ },+ {+ "number": "48",+ "name": "DRVDD",+ "type": "power_in",+ "description": "Output buffer supply, 1.7 V to 1.9 V (1.8 V nominal)."+ },+ {+ "number": "49",+ "name": "DRGND",+ "type": "power_in",+ "description": "Output buffer ground; the PowerPAD is connected to DRGND."+ },+ {+ "number": "50",+ "name": "DA6M",+ "type": "output",+ "description": "Channel A LVDS differential output data D6/D7 multiplexed, complement; in CMOS mode this pin is DA6 (CMOS data bit D6)."+ },+ {+ "number": "51",+ "name": "DA6P",+ "type": "output",+ "description": "Channel A LVDS differential output data D6/D7 multiplexed, true; in CMOS mode this pin is DA7 (CMOS data bit D7)."+ },+ {+ "number": "52",+ "name": "DA8M",+ "type": "output",+ "description": "Channel A LVDS differential output data D8/D9 multiplexed, complement; in CMOS mode this pin is DA8 (CMOS data bit D8)."+ },+ {+ "number": "53",+ "name": "DA8P",+ "type": "output",+ "description": "Channel A LVDS differential output data D8/D9 multiplexed, true; in CMOS mode this pin is DA9 (CMOS data bit D9)."+ },+ {+ "number": "54",+ "name": "DA10M",+ "type": "output",+ "description": "Channel A LVDS differential output data D10/D11 multiplexed, complement; in CMOS mode this pin is DA10 (CMOS data bit D10)."+ },+ {+ "number": "55",+ "name": "DA10P",+ "type": "output",+ "description": "Channel A LVDS differential output data D10/D11 multiplexed, true; in CMOS mode this pin is DA11 (CMOS data bit D11)."+ },+ {+ "number": "56",+ "name": "CLKOUTM",+ "type": "output",+ "description": "Differential LVDS output clock, complement; in CMOS mode this pin is UNUSED."+ },+ {+ "number": "57",+ "name": "CLKOUTP",+ "type": "output",+ "description": "Differential LVDS output clock, true; in CMOS mode this pin is CLKOUT, the CMOS output clock."+ },+ {+ "number": "58",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect; must be floated."+ },+ {+ "number": "59",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect; must be floated."+ },+ {+ "number": "60",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect; must be floated."+ },+ {+ "number": "61",+ "name": "NC",+ "type": "unconnected",+ "description": "Do not connect; must be floated."+ },+ {+ "number": "62",+ "name": "DB0M",+ "type": "output",+ "description": "Channel B LVDS differential output data D0/D1 multiplexed, complement; in CMOS mode this pin is DB0 (CMOS data bit D0)."+ },+ {+ "number": "63",+ "name": "DB0P",+ "type": "output",+ "description": "Channel B LVDS differential output data D0/D1 multiplexed, true; in CMOS mode this pin is DB1 (CMOS data bit D1)."+ },+ {+ "number": "64",+ "name": "SDOUT",+ "type": "output",+ "description": "Serial register readout output when READOUT is enabled, CMOS levels from DRVDD; high-impedance when READOUT = 0."+ },+ {+ "number": "65",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet gives two pin-function tables (LVDS mode and CMOS mode) for the same 64-pin RGC packag; The LVDS-mode pin-function table in the text does not list SEN, but the top-view diagram and the CMO; The extracted LVDS-mode AVDD row reads '23 34', but the top-view diagram and CMOS table place AVDD o",+ "exposed pad 65 added from the footprint"+ ],+ "pages_sent": 22,+ "cost_usd": 0.1545,+ "at": "2026-10-08T15:58:49"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/ads4229",+ "pages": 68,+ "sha256": "47833104b1baa2ae",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 65,+ "described": 65,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "ads4229irgct.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "dce07a86ec3fe3ca87eebdff13827f55e036ced5518fee01f85cec4a3f56366d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "ads4229irgct-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "c1308defc9bd607a2e410a3df3d49855fe4d3cd218fb8b0db80c324ccf1f44ff",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}