# ADS41B49IRGZR

**Texas Instruments** · Analog To Digital Converters (ADC) · VQFN-48-EP(7x7)

ADS41B49IRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DRGND | power_in | Digital and output buffer ground. |
| 2 | DRVDD | power_in | 1.8-V digital and output buffer supply; absolute maximum range is -0.3 V to 2.1 V. |
| 3 | OVR_SDOUT | output | Out-of-range indicator after reset (READOUT = 0) and serial register readout pin when READOUT = 1; a 1.8-V CMOS output running off DRVDD. |
| 4 | CLKOUTM | output | Differential output clock, complement. |
| 5 | CLKOUTP | output | Differential output clock, true. |
| 6 | DFS | input | Data format select input that sets the data format (two's complement or offset binary) and the LVDS or CMOS output interface type. |
| 7 | OE | input | Output buffer enable input, active high; has an internal 100-kΩ pull-up resistor to DRVDD. |
| 8 | AVDD | power_in | 1.8-V analog power supply; absolute maximum range is -0.3 V to 2.1 V. |
| 9 | AGND | power_in | Analog ground. |
| 10 | CLKP | input | Differential clock input, positive. |
| 11 | CLKM | input | Differential clock input, negative. |
| 12 | AGND | power_in | Analog ground. |
| 13 | VCM | output | Outputs the common-mode voltage that can be used externally to bias the analog input pins. |
| 14 | AGND | power_in | Analog ground. |
| 15 | INP | input | Differential analog input, positive; absolute input voltage range is -0.3 V to the minimum of 1.9 V or AVDD + 0.3 V. |
| 16 | INM | input | Differential analog input, negative; absolute input voltage range is -0.3 V to the minimum of 1.9 V or AVDD + 0.3 V. |
| 17 | AGND | power_in | Analog ground. |
| 18 | AVDD | power_in | 1.8-V analog power supply; absolute maximum range is -0.3 V to 2.1 V. |
| 19 | AGND | power_in | Analog ground. |
| 20 | AVDD | power_in | 1.8-V analog power supply; absolute maximum range is -0.3 V to 2.1 V. |
| 21 | AVDD_BUF | power_in | 3.3-V input buffer supply; absolute maximum range is -0.3 V to 3.9 V. |
| 22 | AVDD | power_in | 1.8-V analog power supply; absolute maximum range is -0.3 V to 2.1 V. |
| 23 | RESERVED | input | Digital control pin reserved for future use. |
| 24 | AVDD | power_in | 1.8-V analog power supply; absolute maximum range is -0.3 V to 2.1 V. |
| 25 | AGND | power_in | Analog ground. |
| 26 | AVDD | power_in | 1.8-V analog power supply; absolute maximum range is -0.3 V to 2.1 V. |
| 27 | SEN | input | Serial interface enable input when RESET is low; when RESET is high it has no function and must be tied to AVDD (internal 180-kΩ pull-up to AVDD). |
| 28 | SDATA | input | Serial interface data input when RESET is low; when RESET is high it functions as the STANDBY control pin (internal 180-kΩ pull-down). |
| 29 | SCLK | input | Serial interface clock input when RESET is low; when RESET is high it must be tied to ground (internal 180-kΩ pull-down). |
| 30 | RESET | input | Serial interface reset input; a high pulse wider than 10 ns initializes the registers, and it has an internal 100-kΩ pull-down resistor. |
| 31 | NC | unconnected | Do not connect. |
| 32 | NC | unconnected | Do not connect. |
| 33 | D0_D1_M | output | Differential output data D0 and D1 multiplexed, complement. |
| 34 | D0_D1_P | output | Differential output data D0 and D1 multiplexed, true. |
| 35 | DRVDD | power_in | 1.8-V digital and output buffer supply; absolute maximum range is -0.3 V to 2.1 V. |
| 36 | DRGND | power_in | Digital and output buffer ground. |
| 37 | D2_D3_M | output | Differential output data D2 and D3 multiplexed, complement. |
| 38 | D2_D3_P | output | Differential output data D2 and D3 multiplexed, true. |
| 39 | D4_D5_M | output | Differential output data D4 and D5 multiplexed, complement. |
| 40 | D4_D5_P | output | Differential output data D4 and D5 multiplexed, true. |
| 41 | D6_D7_M | output | Differential output data D6 and D7 multiplexed, complement. |
| 42 | D6_D7_P | output | Differential output data D6 and D7 multiplexed, true. |
| 43 | D8_D9_M | output | Differential output data D8 and D9 multiplexed, complement. |
| 44 | D8_D9_P | output | Differential output data D8 and D9 multiplexed, true. |
| 45 | D10_D11_M | output | Differential output data D10 and D11 multiplexed, complement. |
| 46 | D10_D11_P | output | Differential output data D10 and D11 multiplexed, true. |
| 47 | D12_D13_M | output | Differential output data D12 and D13 multiplexed, complement. |
| 48 | D12_D13_P | output | Differential output data D12 and D13 multiplexed, true. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Data Acquisition |
| Pins | 49 |

## CAD (KiCad official)

- Symbol: `ADS41B49IRGZR`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `ads41b49irgzr-etched.step` / `ads41b49irgzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads41b49irgzr.step` / `ads41b49irgzr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ads41b29) (60 pp, sha256 `15091f6f2adf57af`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ads41b49irgzr-datasheet.pdf)