ADS1283IRHFR

{
  "slug": "ads1283irhfr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Analog To Digital Converters (ADC), VQFN-24-EP(4x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "data acquisition",
    "ads1283irhfr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ads1283irhfr.kicad_sym",
    "ads1283irhfr.kicad_mod",
    "ads1283irhfr.glb",
    "ads1283irhfr.step",
    "ads1283irhfr.lbr",
    "docs/hero.png",
    "docs/ads1283irhfr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "component": {
    "mpn": "ADS1283IRHFR",
    "manufacturer": "Texas Instruments",
    "package": "VQFN-24-EP(4x5)",
    "pin_count": 25,
    "category": "Data Acquisition",
    "subcategory": "Analog To Digital Converters (ADC)",
    "datasheet": "https://www.ti.com/cn/lit/gpn/ads1283",
    "parts": {
      "symbol": "ads1283irhfr.kicad_sym",
      "footprint": "ads1283irhfr.kicad_mod",
      "model_3d": "ads1283irhfr-etched.glb",
      "model_3d_plain": "ads1283irhfr.glb",
      "model_3d_step": "ads1283irhfr-etched.step",
      "model_3d_step_plain": "ads1283irhfr.step",
      "lbr": "ads1283irhfr.lbr"
    },
    "distributor_links": {
      "lcsc": "C1855752"
    },
    "pins": [
      {
        "number": "1",
        "name": "DRDY",
        "type": "output",
        "description": "Data ready output, active low, pulses to indicate new conversion data available."
      },
      {
        "number": "2",
        "name": "DOUT",
        "type": "tri_state",
        "description": "Serial interface data output, tri-state output high impedance when CS is high."
      },
      {
        "number": "3",
        "name": "DIN",
        "type": "input",
        "description": "Serial interface data input, data clocked in on rising edge of SCLK."
      },
      {
        "number": "4",
        "name": "CS",
        "type": "input",
        "description": "Serial interface chip select, active low, enables ADC serial interface when low."
      },
      {
        "number": "5",
        "name": "SYNC",
        "type": "input",
        "description": "Synchronize input, rising edge active, resets digital filter and modulator."
      },
      {
        "number": "6",
        "name": "MFLAG",
        "type": "output",
        "description": "Modulator overrange flag output, high when differential input exceeds ±100% full-scale."
      },
      {
        "number": "7",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground, tie to digital ground plane for low impedance reference."
      },
      {
        "number": "8",
        "name": "CAPN",
        "type": "output",
        "description": "PGA output negative node, connect 10-nF C0G capacitor from CAPP to CAPN for anti-alias filtering."
      },
      {
        "number": "9",
        "name": "CAPP",
        "type": "output",
        "description": "PGA output positive node, connect 10-nF C0G capacitor from CAPP to CAPN for anti-alias filtering."
      },
      {
        "number": "10",
        "name": "AINP2",
        "type": "input",
        "description": "Positive analog input 2, input range AVSS + 0.7 V to AVDD - 1.25 V."
      },
      {
        "number": "11",
        "name": "AINN2",
        "type": "input",
        "description": "Negative analog input 2, input range AVSS + 0.7 V to AVDD - 1.25 V."
      },
      {
        "number": "12",
        "name": "AINP1",
        "type": "input",
        "description": "Positive analog input 1, input range AVSS + 0.7 V to AVDD - 1.25 V."
      },
      {
        "number": "13",
        "name": "AINN1",
        "type": "input",
        "description": "Negative analog input 1, input range AVSS + 0.7 V to AVDD - 1.25 V."
      },
      {
        "number": "14",
        "name": "AVDD",
        "type": "power_in",
        "description": "Positive analog power supply, 4.75 V to 5.25 V above AVSS for unipolar or ±2.5 V operation."
      },
      {
        "number": "15",
        "name": "AVSS",
        "type": "power_in",
        "description": "Negative analog power supply, -2.6 V to 0 V relative to DGND."
      },
      {
        "number": "16",
        "name": "VREFN",
        "type": "input",
        "description": "Negative reference voltage input, range AVSS - 0.1 V to VREFP - 1 V, typical 1 V to 5 V."
      },
      {
        "number": "17",
        "name": "VREFP",
        "type": "input",
        "description": "Positive reference voltage input, range VREFN + 1 V to AVDD + 0.1 V."
      },
      {
        "number": "18",
        "name": "PWDN",
        "type": "input",
        "description": "Power-down input, active low, disables internal circuitry to minimize power dissipation."
      },
      {
        "number": "19",
        "name": "RESET",
        "type": "input",
        "description": "Reset input, active low, resets registers to default and restarts conversion process."
      },
      {
        "number": "20",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital power supply, 1.65 V to 3.6 V, separate from analog supplies."
      },
      {
        "number": "21",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground, tie to digital ground plane for low impedance reference."
      },
      {
        "number": "22",
        "name": "BYPAS",
        "type": "output",
        "description": "1.8-V sub-regulator output, connect 1-μF ceramic capacitor to DGND for noise reduction."
      },
      {
        "number": "23",
        "name": "CLK",
        "type": "input",
        "description": "Master clock input, nominal 4.096 MHz, requires low-jitter crystal oscillator source."
      },
      {
        "number": "24",
        "name": "SCLK",
        "type": "input",
        "description": "Serial interface shift clock input, clocks data into DIN and out of DOUT on rising and falling edges."
      },
      {
        "number": "25",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.2",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.2",
        "primary_model": "claude-haiku-4-5-20251001",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: BYPAS pin has application requirement: DVDD should be tied to BYPAS only if DVDD < 2.25V (see page 3; AVSS can operate from 0V (tied to DGND) down to -2.6V relative to DGND (page 5). Verify analog suppl; CAPP and CAPN require matched external 10-nF C0G or film capacitor and proper PCB layout for optimal",
          "exposed pad 25 added from the footprint"
        ],
        "pages_sent": 68,
        "cost_usd": 0.6244,
        "at": "2026-09-23T04:01:32"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/ads1283",
        "pages": 68,
        "sha256": "a109452d7280f730",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 25,
        "described": 25,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "file": "ads1283irhfr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          4.0,
          5.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "dd34955bd2f41c7d5d4f45257df2b8077e42f694598de69e58ad55ad191eecae",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ads1283irhfr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "c934c9d8f9a41140f376d710939e7e427afa012a9cc7f0cf9006a7b7e394703e",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}